Tyler David Parent

US Patent:

20130168850, Jul 4, 2013

Filed:

Jan 3, 2012

Appl. No.:

13/342420

Inventors:

Arkadii V. Samoilov - Saratoga CA, US
Tyler Parent - Pleasanton CA, US
Larry Y. Wang - San Jose CA, US

Assignee:

MAXIM INTEGRATED PRODUCTS, INC. - Sunnyvale CA

International Classification:

H01L 23/48
H01L 21/56

US Classification:

257737, 438118, 257E23023, 257E21502

Abstract:

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

US Patent:

20130037948, Feb 14, 2013

Filed:

Aug 9, 2011

Appl. No.:

13/205682

Inventors:

Arkadii V. Samoilov - Saratoga CA, US
Tyler Parent - Pleasanton CA, US
Xuejun Ying - San Jose CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 23/485
H01L 21/28

US Classification:

257738, 438667, 257E23011, 257E23021, 257E21158

Abstract:

Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

US Patent:

20160079197, Mar 17, 2016

Filed:

Nov 23, 2015

Appl. No.:

14/948664

Inventors:

- San Jose CA, US
Arkadii V. Samoilov - Saratoga CA, US
Peter McNally - Saratoga CA, US
Tyler Parent - Portland OR, US

International Classification:

H01L 23/00
H01L 21/306
H01L 23/31
H01L 21/683
H01L 23/538
H01L 23/532

Abstract:

Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

US Patent:

20140284793, Sep 25, 2014

Filed:

Jun 9, 2014

Appl. No.:

14/299076

Inventors:

- San Jose CA, US
Tyler Parent - Beaverton OR, US
Larry Y. Wang - San Jose CA, US

International Classification:

H01L 23/00
H01L 23/498

US Classification:

257737, 438118

Abstract:

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

US Patent:

20140264844, Sep 18, 2014

Filed:

Jun 28, 2013

Appl. No.:

13/930417

Inventors:

- San Jose CA, US
Arkadii V. Samoilov - Saratoga CA, US
Peter McNally - Saratoga CA, US
Tyler Parent - Pleasanton CA, US

International Classification:

H01L 23/538
H01L 21/56
H01L 23/498

US Classification:

257737, 257774, 438118

Abstract:

Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.