Urusa S Alaan

US Patent:

20230113614, Apr 13, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485185

Inventors:

- Santa Clara CA, US
Chelsey DOROW - Portland OR, US
Carl NAYLOR - Portland OR, US
Kirby MAXEY - Hillsboro OR, US
Sudarat LEE - Hillsboro OR, US
Ashish Verma PENUMATCHA - Beaverton OR, US
Uygar E. AVCI - Portland OR, US
Scott B. CLENDENNING - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Tristan A. TRONIC - Aloha OR, US

International Classification:

H01L 29/423
H01L 29/786
H01L 27/12

Abstract:

Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.

US Patent:

20230095402, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485190

Inventors:

- Santa Clara CA, US
Elijah V. KARPOV - Portland OR, US
Mohit K. HARAN - Hillsboro OR, US
Reken PATEL - Portland OR, US
Charles H. WALLACE - Portland OR, US
Gurpreet SINGH - Portland OR, US
Florian GSTREIN - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Leonard P. GULER - Hillsboro OR, US
Paul A. NYHUS - Portland OR, US

International Classification:

H01L 21/768
H01L 29/78
H01L 23/535
H01L 29/66

Abstract:

Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

US Patent:

20230101212, Mar 30, 2023

Filed:

Sep 30, 2022

Appl. No.:

17/958295

Inventors:

- Santa Clara CA, US
Elijah V. KARPOV - Portland OR, US
Mohit K. HARAN - Hillsboro OR, US
Reken PATEL - Portland OR, US
Charles H. WALLACE - Portland OR, US
Gurpreet SINGH - Portland OR, US
Florian GSTREIN - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Leonard P. GULER - Hillsboro OR, US
Paul A. NYHUS - Portland OR, US

International Classification:

H01L 21/768
H01L 29/66
H01L 23/535
H01L 29/78

Abstract:

Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

US Patent:

20230090093, Mar 23, 2023

Filed:

Sep 20, 2021

Appl. No.:

17/479769

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Chelsey DOROW - Portland OR, US
Tanay GOSAVI - Portland OR, US
Chia-Ching LIN - Portland OR, US
Carl NAYLOR - Portland OR, US
Kevin P. O'BRIEN - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Ian A. YOUNG - Olympia WA, US
Urusa ALAAN - Hillsboro OR, US

International Classification:

H01L 29/423
H01L 29/10
H01L 29/08

Abstract:

Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.

US Patent:

20230081882, Mar 16, 2023

Filed:

Sep 14, 2021

Appl. No.:

17/474689

Inventors:

- Santa Clara CA, US
Abhishek A. Sharma - Portland OR, US
Aaron D. Lilak - Beaverton OR, US
Hui Jae Yoo - Hillsboro OR, US
Scott B. Clendenning - Portland OR, US
Van H. Le - Beaverton OR, US
Tristan A. Tronic - Aloha OR, US
Urusa Alaan - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/108
H01L 27/06
G11C 5/10

Abstract:

A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

US Patent:

20230073078, Mar 9, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/445856

Inventors:

- Santa Clara CA, US
Sudipto Naskar - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Gilbert Dewey - Beaverton OR, US
Marko Radosavljevic - Portland OR, US
Nicole K. Thomas - Portland OR, US
Patrick Morrow - Portland OR, US
Urusa Alaan - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/12

Abstract:

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

US Patent:

20210407999, Dec 30, 2021

Filed:

Jun 26, 2020

Appl. No.:

16/913796

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Beaverton OR, US
Anh PHAN - Beaverton OR, US
Nicole K. THOMAS - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Seung Hoon SUNG - Portland OR, US
Christopher M. NEUMANN - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Patrick MORROW - Portland OR, US
Hui Jae YOO - Portland OR, US
Richard E. SCHENKER - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Ehren MANNEBACH - Beaverton OR, US

International Classification:

H01L 27/092
H01L 29/06
H01L 29/78
H01L 29/775
H01L 29/423

Abstract:

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

US Patent:

20210375873, Dec 2, 2021

Filed:

Jun 1, 2020

Appl. No.:

16/888910

Inventors:

- Santa Clara CA, US
Abhishek A. Sharma - Hillsboro OR, US
Charles Kuo - Union City CA, US
Brian S. Doyle - Portland OR, US
Urusa Shahriar Alaan - Hillsboro OR, US
Van H. Le - Beaverton OR, US
Elijah V. Karpov - Portland OR, US
Kaan Oguz - Portland OR, US
Arnab Sen Gupta - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/108
H01L 25/065

Abstract:

Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.