Ven Chung Lee

US Patent:

55008054, Mar 19, 1996

Filed:

Sep 2, 1994

Appl. No.:

8/300637

Inventors:

Ven L. Lee - Los Altos Hills CA
William M. Dawson - San Jose CA
Donald L. Doud - Spring TX

Assignee:

Nsoft Systems, Inc. - Santa Clara CA
Compaq Computer Corporation - Houston TX

International Classification:

G06F 1750

US Classification:

364491

Abstract:

In accordance with the teachings of this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

US Patent:

55109993, Apr 23, 1996

Filed:

Sep 2, 1994

Appl. No.:

8/300636

Inventors:

Ven L. Lee - Los Altos Hills CA
William M. Dawson - San Jose CA

Assignee:

Nsoft Systems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

364491

Abstract:

In accordance with the teachings of this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

US Patent:

55638015, Oct 8, 1996

Filed:

Oct 6, 1993

Appl. No.:

8/132558

Inventors:

Ven L. Lee - Los Altos Hills CA
Hemraj K. Hingarh - Saratoga CA

Assignee:

nSOFT Systems, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

364491

Abstract:

A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.