Veronica Alarcon

US Patent:

20130044844, Feb 21, 2013

Filed:

Dec 27, 2011

Appl. No.:

13/338001

Inventors:

Love KOTHARI - Sunnyvale CA, US
Mark FULLERTON - Austin TX, US
Rajesh RAJAN - Bangalore, IN
Veronica ALARCON - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/02

US Classification:

375360, 375359

Abstract:

An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

US Patent:

20130047000, Feb 21, 2013

Filed:

Apr 2, 2012

Appl. No.:

13/437675

Inventors:

Veronica ALARCON - San Jose CA, US
Love Kothari - Sunnyvale CA, US
Amar Guettaf - Sunnyvale CA, US
Kerry Thompson - Fort Collins CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit, Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

US Patent:

20030120922, Jun 26, 2003

Filed:

Dec 4, 2002

Appl. No.:

10/310374

Inventors:

NI Sun - Sunnyvale CA, US
Collin Connors - San Jose CA, US
Veronica Alarcon - San Jose CA, US
Hassan Hanjani - Fremont CA, US

Assignee:

Fairchild Semiconductor Corporation

International Classification:

H04L009/00

US Classification:

713/168000

Abstract:

A system and method for device authentication are disclosed. In one embodiment, a random security code is generated during a boot operation to verify authenticity of a device. The random security code may comprise a rolling code based on a static number and a seed number, where the static number does not change between successive boots and the seed number changes between boots. A random number generator algorithm may provide the seed number.

US Patent:

20140218078, Aug 7, 2014

Filed:

Jul 25, 2013

Appl. No.:

13/950769

Inventors:

- Irvine CA, US
Veronica Alarcon - San Jose CA, US
Mark Norman Fullerton - Austin TX, US
Ajmal A. Godil - San Diego CA, US
Zhongmin Zhang - Fremont CA, US

International Classification:

G05F 1/625

US Classification:

327143

Abstract:

Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.