Master of Business Administration in Marketing & Supply Chain
Skills
Technology: Microsoft Office (Word • PowerPoint • Excel • Access • Outlook) • QuickBooks • and Simmons OneView; Language: Spanish (... • French (conversant) • Italian (conversant); Experienced domest... • including study abroad in Central and Ea...
Texas Instruments Jan 2016 - Nov 2016
Worldwide Procurement and Logistics Finance Analyst
Texas Instruments Jan 2015 - Jan 2016
Management Accountant
Texas Instruments Jan 2014 - Jan 2015
Worldwide Business Planner
Classic Travel, Inc. Aug 2013 - Dec 2013
Intern
Spartan Consulting, Inc. Aug 2012 - Dec 2012
Consultant
Education:
Michigan State University 2013
Master of Business Administration, Masters
Michigan State University - the Eli Broad College of Business 2011 - 2013
Master of Business Administration, Masters, Bachelors, Bachelor of Arts, Marketing
Hampton University 2007 - 2011
Bachelors, Bachelor of Science, Accounting, Spanish
Woodward Academy 2000 - 2007
Skills:
Leadership Social Media Marketing Microsoft Office Microsoft Excel Management Powerpoint Analysis Accounting Teamwork Microsoft Word Data Analysis Time Management Event Planning Spanish Social Networking Project Management Customer Service Financial Reporting Negotiation Facebook Financial Analysis Cross Functional Team Leadership Fundraising International Business Sales Marketing Strategy Market Research Team Building Public Speaking Travel Management Travel Planning World Travel Press Releases Public Relations Crm Competitive Analysis
Syed Hasan Yousuf - Saratoga CA Veronica Collaco Stewart - San Jose CA Hai Xuan Nguyen - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R 3128
US Classification:
714724
Abstract:
A method for improving the fault coverage of functional tests for integrated circuits by establishing a design-specific low voltage functional screening procedure. In the disclosed embodiment of the invention, a reduced voltage test threshold is established by comparing the results of an iterative test procedure executed on a set of known good integrated circuits and integrated circuits which have passed traditional functional test programs but manifested problems in the field. For a given device under test, the iterative procedure commences by applying a system clock and nominal power supply voltage. A set of functional test vectors is then executed on the device using automated test equipment (ATE). The results are compared with expected test results to determine if the device is a passing device under the initial test conditions. If so, the power supply voltage is decremented by a predetermined value and the test process is repeated.