Victor M Dacosta

US Patent:

6625560, Sep 23, 2003

Filed:

Jul 13, 2001

Appl. No.:

09/904783

Inventors:

Ziaus S. Molla - Santa Clara CA
Victor DaCosta - Santa Cruz CA
Seung Ho Hwang - Palo Alto CA
Baegin Sung - Sunnyvale CA

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

G06F 1100

US Classification:

702120, 702125, 714731, 714814

Abstract:

A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

US Patent:

57036217, Dec 30, 1997

Filed:

Jul 12, 1996

Appl. No.:

8/679168

Inventors:

Russel A. Martin - Menlo Park CA
Richard H. Bruce - Los Altos CA
Victor M. DaCosta - San Carlos CA
Thomas G. Fiske - Campbell CA
Alan G. Lewis - Sunnyvale CA
Louis D. Silverstein - Scottsdale AZ
Hugo L. Steemers - Palo Alto CA
Malcolm J. Thompson - Palo Alto CA
William D. Turner - San Marino CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G09G 510

US Classification:

345147

Abstract:

An array of light control units has an area large enough to present images for direct viewing. The array also has light control units sufficiently dense that ordinary acuity artifacts are not noticeable in presented images when the array is directly viewed at usual viewing distances by a human with normal vision. Signal circuitry can provide signals to the light control units. The array can present an image that includes M colors, where M is more than three, even though each light control unit can only cause presentation of one of a segment with one of a set of N colors, where N is less than M. Data defining an input image with M colors are used to obtain data defining an output image that is a version of the input image but includes, for each light control unit, a color data item indicating one of its set of N colors. The signal circuitry provides signals to the light control units so that each light control unit presents a segment with the color indicated by its color data item. As a result, the array presents the output image so that its appearance to a human with normal vision viewing the array at usual viewing distances is substantially identical to the appearance the input image would have if presented.

US Patent:

62818910, Aug 28, 2001

Filed:

Jun 2, 1995

Appl. No.:

8/458539

Inventors:

Victor M. DaCosta - San Jose CA
Alan G. Lewis - Sunnyvale CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G09G 500

US Classification:

345206

Abstract:

A product such as a display includes a first substrate on which array circuitry and multiplexer circuitry are formed and also includes one or more integrated circuit (IC) structures attached to the first substrate. The array circuitry includes N data lines, each driven by multiplexed signals, where N is greater than 32. The multiplexer circuitry provides the multiplexed signals in response to analog drive signals from P analog input leads and multiplexer control signals from Q control leads, where P is less than N but not less than 32 and where Q is less than N but not less than N/P. Each of R IC structures can includes a single crystal substrate, each with digital-to-analog converting (DAC) circuitry, where R is greater than zero. Each substrate has at least S analog output leads, where S is not less than 32. Together, the R IC structures have T analog output leads, where T is greater than P, and each of the P analog input leads is paired with and connected to one of the T analog output leads.

US Patent:

56549709, Aug 5, 1997

Filed:

Dec 22, 1995

Appl. No.:

8/575784

Inventors:

Victor M. DaCosta - Santa Cruz CA
Duane Siemens - Redwood City CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G01R 3128

US Classification:

371 2231

Abstract:

An array includes redundant integrated scan drivers that can provide signals to each other through scan lines. Each scan driver can be a shift register, each stage of which includes a tri-state inverter to provide its output to one of the scan lines. To transfer signals from one shift register to the other, one shift register provides signals while the outputs of the other shift register are in a floating state. The other shift register receives the signals and can then shift them to its output. The signals can be test signals used to detect defects in the shift registers and in the array. Also, each stage in each shift register is connected to receive signals from the scan line that is driven by the preceding stage. Therefore, if the preceding stage is removed due to a defect, the following stage can receive signals through the scan line from the other shift register and continue to function even though its preceding stage is removed.