Victor A Holen

US Patent:

62126393, Apr 3, 2001

Filed:

Jun 29, 1999

Appl. No.:

9/342336

Inventors:

Charles R. Erickson - Fremont CA
Danesh Tavana - Mountain View CA
Victor A. Holen - Los Gatos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04K 100

US Classification:

713200

Abstract:

A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.

US Patent:

58835253, Mar 16, 1999

Filed:

Oct 3, 1997

Appl. No.:

8/943890

Inventors:

Danesh Tavana - Mountain View CA
Wilson K. Yee - Tracy CA
Victor A. Holen - Saratoga CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 738
H03K 19177

US Classification:

326 39

Abstract:

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

US Patent:

56821077, Oct 28, 1997

Filed:

Mar 19, 1996

Appl. No.:

8/618445

Inventors:

Danesh Tavana - Mountain View CA
Wilson K. Yee - Tracy CA
Victor A. Holen - Saratoga CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.