Victor Kin Suen

US Patent:

7239170, Jul 3, 2007

Filed:

Jul 8, 2003

Appl. No.:

10/614956

Inventors:

Victor Suen - Fremont CA, US
William Lau - Foster City CA, US
Cheng-Gang Kong - Saratoga CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 326 86

Abstract:

Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

US Patent:

20040260962, Dec 23, 2004

Filed:

Jun 23, 2003

Appl. No.:

10/601441

Inventors:

Victor Suen - Fremont CA, US
William Lau - Foster City CA, US
Hui-Yin Seto - San Jose CA, US

International Classification:

G06F001/12

US Classification:

713/401000

Abstract:

Systems and methods are provided for latching a data signal. In one embodiment, a system comprises a first delay circuit that programmably delays a strobe signal with a first delay to latch a data signal. The system also comprises a second delay circuit that receives the data signal and delays the data signal with a second delay that is substantially inherent to the first delay. The system may include a logic circuit coupled between the first and the second delay circuits for latching the data signal in substantial alignment with the strobe signal. In one embodiment, similar delays are used in a master delay circuit, while in another embodiment such delays are used in slave devices connected to a master delay circuit.

US Patent:

20060132210, Jun 22, 2006

Filed:

Dec 22, 2004

Appl. No.:

11/021361

Inventors:

Cheng-Gang Kong - Saratoga CA, US
Victor Suen - Fremont CA, US

International Classification:

H03H 11/26

US Classification:

327261000

Abstract:

An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

US Patent:

20120128097, May 24, 2012

Filed:

Nov 24, 2010

Appl. No.:

12/954028

Inventors:

Thomas Hughes - San Francisco CA, US
Victor K. Suen - Fremont CA, US

International Classification:

H04L 25/49

US Classification:

375296

Abstract:

Transmitter-based techniques are provided for compensation of intersymbol interference and/or simultaneous switching outputs, using selective pulse width modulation. One or more signals are transmitted by detecting whether one or more of said signals satisfy one or more predefined signal corruption conditions, wherein said predefined signal corruption conditions indicate that one or more of said signals are anticipated to exhibit one or more of intersymbol interference and simultaneous switching outputs; and selecting a delay for one or more of the signals based on the one or more predefined signal corruptions conditions. The predefined signal corruption conditions comprise, for example, (i) digital data encoded in the one or more signals maintaining a same binary value for two or more consecutive clock cycles (to indicate intersymbol interference); and (ii) a predefined minimum number of aggressor data edges in digital data encoded in the one or more signals, and a corresponding predefined number of victim data edges in the digital data encoded in the one or more signals, wherein the victim edges are moving in an opposite direction to the aggressor data edges (to indicate simultaneous switching outputs).