Vidya S Kaushik

US Patent:

6448192, Sep 10, 2002

Filed:

Apr 16, 2001

Appl. No.:

09/835770

Inventors:

Vidya S. Kaushik - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2131

US Classification:

438785, 438761, 438762, 438765, 438770, 438778, 438779, 438787

Abstract:

Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

US Patent:

6518106, Feb 11, 2003

Filed:

May 26, 2001

Appl. No.:

09/865855

Inventors:

Tat Ngai - Austin TX
Vidya S. Kaushik - Austin TX
Jamie K. Schaeffer - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2100

US Classification:

438157, 438176, 438583, 257250, 257331, 257388, 257407, 257412

Abstract:

A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

US Patent:

6518634, Feb 11, 2003

Filed:

Sep 1, 2000

Appl. No.:

09/654704

Inventors:

Vidya S. Kaushik - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2976

US Classification:

257406, 257410, 257411, 257310, 438216, 438261, 438287

Abstract:

A method of forming a capacitor and transistor are disclosed. Initially, a substrate having a semiconductor material on a first surface is provided. A layer of strontium nitride is then deposited over the first surface and a gate electrode formed over the strontium nitride. Source and drains are then formed in the first surface disposed laterally adjacent to the gate electrode to leave a channel under the gate electrode. A dielectric layer may be formed over the layer of strontium nitride prior to forming the gate electrode. The dielectric layer may include strontium, titanium, and oxygen. In one embodiment, the dielectric layer and the layer of strontium nitride are epitaxial layers. In another embodiment the layer of strontium nitride is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). The dielectric layer may include strontium, oxygen, and nitrogen, such as strontium oxynitride formed by sputtering, CVD, or ALD.

US Patent:

57121770, Jan 27, 1998

Filed:

Sep 25, 1995

Appl. No.:

8/533496

Inventors:

Vidya S. Kaushik - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 218247
H01L 21316

US Classification:

437 42

Abstract:

An embodiment of the invention allows the reversing of the sequence of a stacked gate dielectric layer so that a thermal oxide overlies a CVD deposited oxide. A CVD dielectric (12) is first deposited to a desired thickness. Then a layer of silicon (16), either amorphous or polycrystalline, is deposited overlying the CVD dielectric, wherein this silicon layer is approximately one-half of the desired thickness of the final top oxide. The silicon layer is then thermally oxidized to form thermal oxide (18). This method of the invention allows the denser thermal oxide to be formed overlying the less dense CVD dielectric layer as desired to form a reverse dielectric stack.

US Patent:

52368521, Aug 17, 1993

Filed:

Sep 24, 1992

Appl. No.:

7/950333

Inventors:

Michael Cherniawski - Austin TX
Jeffrey M. Barker - Manor TX
Ronald E. Pyle - Austin TX
Vidya S. Kaushik - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21283
H01L 21335

US Classification:

437 41

Abstract:

An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

US Patent:

61840726, Feb 6, 2001

Filed:

May 17, 2000

Appl. No.:

9/571588

Inventors:

Vidya S. Kaushik - Austin TX
Olubunmi O. Adetutu - Austin TX
Christopher C. Hobbs - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21336

US Classification:

438197

Abstract:

A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO. sub. 2 or a combination of SiO. sub. 2, SiO. sub. 3 and SiO. sub. 4 (oxide-nitride or oxynitride) stacks.