Vijayalakshmi Srinivasan

US Patent:

7134028, Nov 7, 2006

Filed:

May 1, 2003

Appl. No.:

10/428170

Inventors:

Pradip Bose - Yorktown Heights NY, US
David M. Brooks - Newark DE, US
Peter W. Cook - Mount Kisco NY, US
Philip G. Emma - Danbury CT, US
Michael K. Gschwind - Chappaqua NY, US
Stanley E. Schuster - Granite Springs NY, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713300, 713320

Abstract:

An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

US Patent:

7337271, Feb 26, 2008

Filed:

Dec 1, 2003

Appl. No.:

10/724815

Inventors:

Philip George Emma - Danbury CT, US
Allan Mark Hartstein - Chappaqua NY, US
Brian R. Prasky - Wappingers Falls NY, US
Thomas Roberts Puzak - Ridgefield CT, US
Moinuddin Khalil Ahmed Qureshi - Austin TX, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/00

US Classification:

711117, 711118, 711119, 711122, 712240, 712239, 712238

Abstract:

A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

US Patent:

7366875, Apr 29, 2008

Filed:

Mar 1, 2005

Appl. No.:

11/069014

Inventors:

Galen A. Rasche - Urbana IL, US
Jude A. Rivers - Cortlandt Manor NY, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712205, 711125

Abstract:

A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

US Patent:

7401209, Jul 15, 2008

Filed:

Jun 30, 2006

Appl. No.:

11/427928

Inventors:

Erik R. Altman - Danbury CT, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/312

US Classification:

712225, 711141, 711146, 712216

Abstract:

A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found.

US Patent:

7447923, Nov 4, 2008

Filed:

Aug 19, 2005

Appl. No.:

11/207333

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Zhigang Hu - Ossining NY, US
Hans Mikael Jacobson - White Plains NY, US
Vijayalakshmi Srinivasan - New York NY, US
Victor Zyuban - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32

US Classification:

713300, 713320, 713323, 713330

Abstract:

A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.

US Patent:

7454573, Nov 18, 2008

Filed:

Jan 13, 2005

Appl. No.:

11/035350

Inventors:

Alper Buyuktosunoglu - Putnam Valley NY, US
Zhigang Hu - Ossining NY, US
Jude A. Rivers - Cortlandt Manor NY, US
John T. Robinson - Yorktown Heights NY, US
Xiaowei Shen - Hopewell Junction NY, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711133, 711134, 711136, 711159, 711160

Abstract:

A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.

US Patent:

7472226, Dec 30, 2008

Filed:

Mar 20, 2008

Appl. No.:

12/052163

Inventors:

Philip G. Emma - Danbury CT, US
Robert K. Montoye - Jersey City NJ, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711128, 711118

Abstract:

A method for accessing data in memory comprising, receiving address bits associated with a data item including a first tag, an index, and a sector ID from a requestor, associating the index with a congruence class in a primary directory, determining whether the first tag matches a second tag in a plurality of tags in the congruence class, wherein the each tag of the plurality of tags uniquely identifies a cache line associated with a primary ID in the congruence class, defining the primary ID of the second tag of the primary directory that matches the first tag, determining whether the primary ID and the sector ID are present in a secondary directory entry having a one to one correspondence with a sector in a data array, and sending the data item from the sector to the requestor.

US Patent:

7493480, Feb 17, 2009

Filed:

Jul 18, 2002

Appl. No.:

10/197714

Inventors:

Philip G. Emma - Danbury CT, US
Klaus J. Getzlaff - Schonaich, DE
Allan M. Hartstein - Chappaqua NY, US
Thomas Pflueger - Leinfelden, DE
Thomas R. Puzak - Ridgefield CT, US
Eric Mark Schwarz - Gardiner NY, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/00

US Classification:

712240

Abstract:

A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.