Vijayalakshmi K Srinivasan

US Patent:

20170123794, May 4, 2017

Filed:

Nov 4, 2015

Appl. No.:

14/932629

Inventors:

- Armonk NY, US
Kailash Gopalakrishnan - San Jose CA, US
Jinwook Oh - Edgewater NJ, US
Lee M. Saltzman - Troy NY, US
Sunil K. Shukla - Dobbs Ferry NY, US
Vijayalakshmi Srinivasan - New York NY, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

An apparatus and method for supporting simultaneous multiple iterations (SMI) and iteration level commits (ILC) in a course grained reconfigurable architecture (CGRA). The apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. The processing elements, LSU and control unit are configured to commit instructions, and save and restore context at loop iteration boundaries. In doing so, the apparatus tracks and buffers state of in-flight iterations, and detects conditions that prevents an iteration from completion. In support of ILC functions, the LSU is iteration aware and includes: an iteration-interleaved LSQ banks; a Bloom Filter for filtering instructions; a load coalescing buffer.

US Patent:

20170123795, May 4, 2017

Filed:

Nov 4, 2015

Appl. No.:

14/932672

Inventors:

- Armonk NY, US
Kailash Gopalakrishnan - San Jose CA, US
Jinwook Oh - Edgewater NJ, US
Sunil K. Shukla - Dobbs Ferry NY, US
Vijayalakshmi Srinivasan - New York NY, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

An apparatus and method for supporting simultaneous multiple iterations (SMI) in a course grained reconfigurable architecture (CGRA). In support of SMI, the apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. SMI permits execution of the next instruction within any iteration (in flight). If instructions from multiple iterations are ready for execution (and are pre-decoded), then the hardware selects the lowest iteration number ready for execution. If in a particular clock cycle, a loop iteration with a lower iteration number is stalled (i.e., is waiting for data), the instruction from the next highest iteration number that is ready thereby will be automatically executed automatically allowing the CGRA to have high ILP by overlapping concurrent loop iterations.