Vikas Gupta

US Patent:

6433392, Aug 13, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/456036

Inventors:

E. Ajith Amerasekera - Plano TX
Vikas Gupta - Dallas TX
Stanton P. Ashburn - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257355, 257357, 257369, 257372, 438510, 438518, 438519, 438521, 438529

Abstract:

The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

US Patent:

7456477, Nov 25, 2008

Filed:

Jul 9, 2002

Appl. No.:

10/191902

Inventors:

E. Ajith Amerasekera - Plano TX, US
Vikas Gupta - Dallas TX, US
Stanton P. Ashburn - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/62

US Classification:

257357, 257355

Abstract:

The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

US Patent:

7838988, Nov 23, 2010

Filed:

Aug 19, 2009

Appl. No.:

12/543763

Inventors:

Siva Prakash Gurrum - Irving TX, US
Kapil Heramb Sahasrabudhe - Dallas TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/10
H01L 23/34
H01L 23/12

US Classification:

257720, 257706, 257712, 257713, 257717, 257718, 257E21497, 257E21499, 257E21508, 257E21514, 361688, 361704, 361705, 361707

Abstract:

A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

US Patent:

8129224, Mar 6, 2012

Filed:

Oct 18, 2010

Appl. No.:

12/906240

Inventors:

Siva P Gurrum - Irving TX, US
Kapil H Sahasrabudhe - Dallas TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44

US Classification:

438122, 438106, 438108, 438118, 438612, 257E21497, 257E21499, 257E21508, 257E21514

Abstract:

A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.