Vikas S Gupta

US Patent:

6433392, Aug 13, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/456036

Inventors:

E. Ajith Amerasekera - Plano TX
Vikas Gupta - Dallas TX
Stanton P. Ashburn - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257355, 257357, 257369, 257372, 438510, 438518, 438519, 438521, 438529

Abstract:

The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

US Patent:

6576961, Jun 10, 2003

Filed:

Apr 24, 2002

Appl. No.:

10/131732

Inventors:

Vikas I. Gupta - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257360, 257357, 257358, 257363

Abstract:

An embodiment of the invention is a doped region within the silicon substrate of an integrated circuit where the silicon substrate separates the doped region into at least two sub-regions. Another embodiment of the invention is a method of manufacturing an integrated circuit where any logic element is formed in a doped region. The doped region containing the logic element is separated into at least two sub-regions by the silicon substrate of the integrated circuit.

US Patent:

7456477, Nov 25, 2008

Filed:

Jul 9, 2002

Appl. No.:

10/191902

Inventors:

E. Ajith Amerasekera - Plano TX, US
Vikas Gupta - Dallas TX, US
Stanton P. Ashburn - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/62

US Classification:

257357, 257355

Abstract:

The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

US Patent:

7572679, Aug 11, 2009

Filed:

Jul 26, 2007

Appl. No.:

11/828853

Inventors:

Vikas Gupta - Dallas TX, US
Siva P. Gurrum - Dallas TX, US
Gregory E. Howard - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438124, 438127, 438617, 257E21502

Abstract:

A semiconductor device (A) with plastic encapsulation compound () and metal sheets (and ) on both surfaces, acting as heat spreaders. One or more thermal conductors () of preferably uniform height connect one sheet () and the chip surface (); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (). The substrate (, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

US Patent:

7838988, Nov 23, 2010

Filed:

Aug 19, 2009

Appl. No.:

12/543763

Inventors:

Siva Prakash Gurrum - Irving TX, US
Kapil Heramb Sahasrabudhe - Dallas TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/10
H01L 23/34
H01L 23/12

US Classification:

257720, 257706, 257712, 257713, 257717, 257718, 257E21497, 257E21499, 257E21508, 257E21514, 361688, 361704, 361705, 361707

Abstract:

A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

US Patent:

7892889, Feb 22, 2011

Filed:

Jun 25, 2009

Appl. No.:

12/491667

Inventors:

Gregory E Howard - Dallas TX, US
Vikas Gupta - Dallas TX, US
Darvin R Edwards - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438109, 438127, 257E23001

Abstract:

One embodiment of the invention is a semiconductor system () of arrays (, etc. ) of packaged devices. Each array includes a sheet-like substrate (, etc. ) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (, etc. ), which adheres to the substrate, embeds the connected components. Metal posts (, etc. ) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

US Patent:

7956456, Jun 7, 2011

Filed:

Feb 27, 2008

Appl. No.:

12/038005

Inventors:

Siva Prakash Gurrum - Dallas TX, US
Paul Joseph Hundt - Garland TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/34

US Classification:

257707, 257706, 257717, 257720, 257E33076, 257E31131, 257E23051, 257E23098, 257E23101

Abstract:

An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.

US Patent:

7989949, Aug 2, 2011

Filed:

Jul 8, 2009

Appl. No.:

12/499182

Inventors:

Vikas Gupta - Dallas TX, US
Siva P Gurrum - Dallas TX, US
Gregory E Howard - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/34

US Classification:

257720, 257784, 257787, 257792, 257793, 257E21502, 438612, 438615, 438617, 438106, 438124

Abstract:

A semiconductor device (A) with plastic encapsulation compound () and metal sheets (and ) on both surfaces, acting as heat spreaders. One or more thermal conductors () of preferably uniform height connect one sheet () and the chip surface (); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (). The substrate (, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.