Vikas B Gupta

US Patent:

6576961, Jun 10, 2003

Filed:

Apr 24, 2002

Appl. No.:

10/131732

Inventors:

Vikas I. Gupta - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257360, 257357, 257358, 257363

Abstract:

An embodiment of the invention is a doped region within the silicon substrate of an integrated circuit where the silicon substrate separates the doped region into at least two sub-regions. Another embodiment of the invention is a method of manufacturing an integrated circuit where any logic element is formed in a doped region. The doped region containing the logic element is separated into at least two sub-regions by the silicon substrate of the integrated circuit.

US Patent:

7572679, Aug 11, 2009

Filed:

Jul 26, 2007

Appl. No.:

11/828853

Inventors:

Vikas Gupta - Dallas TX, US
Siva P. Gurrum - Dallas TX, US
Gregory E. Howard - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438124, 438127, 438617, 257E21502

Abstract:

A semiconductor device (A) with plastic encapsulation compound () and metal sheets (and ) on both surfaces, acting as heat spreaders. One or more thermal conductors () of preferably uniform height connect one sheet () and the chip surface (); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (). The substrate (, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

US Patent:

7838988, Nov 23, 2010

Filed:

Aug 19, 2009

Appl. No.:

12/543763

Inventors:

Siva Prakash Gurrum - Irving TX, US
Kapil Heramb Sahasrabudhe - Dallas TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/10
H01L 23/34
H01L 23/12

US Classification:

257720, 257706, 257712, 257713, 257717, 257718, 257E21497, 257E21499, 257E21508, 257E21514, 361688, 361704, 361705, 361707

Abstract:

A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

US Patent:

7892889, Feb 22, 2011

Filed:

Jun 25, 2009

Appl. No.:

12/491667

Inventors:

Gregory E Howard - Dallas TX, US
Vikas Gupta - Dallas TX, US
Darvin R Edwards - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438109, 438127, 257E23001

Abstract:

One embodiment of the invention is a semiconductor system () of arrays (, etc. ) of packaged devices. Each array includes a sheet-like substrate (, etc. ) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (, etc. ), which adheres to the substrate, embeds the connected components. Metal posts (, etc. ) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

US Patent:

7956456, Jun 7, 2011

Filed:

Feb 27, 2008

Appl. No.:

12/038005

Inventors:

Siva Prakash Gurrum - Dallas TX, US
Paul Joseph Hundt - Garland TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/34

US Classification:

257707, 257706, 257717, 257720, 257E33076, 257E31131, 257E23051, 257E23098, 257E23101

Abstract:

An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.

US Patent:

7989949, Aug 2, 2011

Filed:

Jul 8, 2009

Appl. No.:

12/499182

Inventors:

Vikas Gupta - Dallas TX, US
Siva P Gurrum - Dallas TX, US
Gregory E Howard - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/34

US Classification:

257720, 257784, 257787, 257792, 257793, 257E21502, 438612, 438615, 438617, 438106, 438124

Abstract:

A semiconductor device (A) with plastic encapsulation compound () and metal sheets (and ) on both surfaces, acting as heat spreaders. One or more thermal conductors () of preferably uniform height connect one sheet () and the chip surface (); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (). The substrate (, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

US Patent:

8110438, Feb 7, 2012

Filed:

Aug 11, 2006

Appl. No.:

11/463985

Inventors:

Vikas Gupta - Dallas TX, US
Jeremias Perez Libres - Garland TX, US
Joseph Edward Grigalunas - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438106, 438126, 438127, 257E23116

Abstract:

A method and apparatus for assembling a semiconductor device. A chip () with solder bodies () on its contact pads is flipped onto a substrate (). After the reflow process, a gap () spaces chip and substrate apart. A polymer precursor is selected for its viscosity of known temperature dependence. The apparatus has a plate () with heating and cooling means to select and control a temperature profile from location to location across the plate. After preheating, the assembly is placed on a mesa () of the plate configured to heat only a portion of the substrate. Movable capillaries () blow cooled gas onto selected locations of the assembly. After the temperature profile is reached, a quantity of the precursor is deposited at a chip side and pulled into the gap by capillary action. The capillary flow is controlled by controlling the precursor viscosity based on the temperature profile, resulting in a substantially linear front, until the gap is filled substantially without voids.

US Patent:

8129224, Mar 6, 2012

Filed:

Oct 18, 2010

Appl. No.:

12/906240

Inventors:

Siva P Gurrum - Irving TX, US
Kapil H Sahasrabudhe - Dallas TX, US
Vikas Gupta - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44

US Classification:

438122, 438106, 438108, 438118, 438612, 257E21497, 257E21499, 257E21508, 257E21514

Abstract:

A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.