Vinh V Ho

US Patent:

7893726, Feb 22, 2011

Filed:

Jul 24, 2007

Appl. No.:

11/782443

Inventors:

Vinh Van Ho - San Jose CA, US
Tim Tri Hoang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 19/00

US Classification:

327 57, 327 52, 330252, 330277

Abstract:

A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.

US Patent:

8049532, Nov 1, 2011

Filed:

Jun 25, 2010

Appl. No.:

12/823596

Inventors:

Simardeep Maangat - Sunnyvale CA, US
Vinh Van Ho - San Jose CA, US
Tim Tri Hoang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/0175
H03L 5/00

US Classification:

326 68, 327333

Abstract:

A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.

US Patent:

8294500, Oct 23, 2012

Filed:

Nov 18, 2009

Appl. No.:

12/621493

Inventors:

Vinh Van Ho - San Jose CA, US
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Van Ton-That - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 11/16

US Classification:

327231, 327237

Abstract:

A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

US Patent:

8619931, Dec 31, 2013

Filed:

Nov 19, 2009

Appl. No.:

12/622152

Inventors:

Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Thungoc M. Tran - San Jose CA, US
Vinh Van Ho - San Jose CA, US
Leon Zheng - San Francisco CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 7/00

US Classification:

375355

Abstract:

Integrated circuits having transceivers capable of high-speed (e. g. , 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

US Patent:

7994837, Aug 9, 2011

Filed:

Aug 7, 2009

Appl. No.:

12/537634

Inventors:

Vinh Van Ho - San Jose CA, US
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 11/16

US Classification:

327231, 327233

Abstract:

A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

US Patent:

7521964, Apr 21, 2009

Filed:

Mar 26, 2007

Appl. No.:

11/691106

Inventors:

Mei Luo - San Jose CA, US
Vinh Van Ho - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 68, 326 81, 326115

Abstract:

In level-shifting circuitry for shifting low-voltage-domain signals to a high-voltage domain, one of two output transistors is driven with one of the low-voltage-domain signals, thereby reducing loading on the output and increasing output speed and bandwidth. The circuitry can be mirrored for differential operation. When included in a serial interface of a programmable logic device, the circuitry can be programmably selectable between single-ended and differential operation.

US Patent:

20140238858, Aug 28, 2014

Filed:

Feb 25, 2014

Appl. No.:

14/189325

Inventors:

- Oakland CA, US
Victor H. Perez-Gonzalez - Monterrey, MX
Vinh Ho - Fountain Valley CA, US

Assignee:

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

International Classification:

C25D 15/00

US Classification:

204477

Abstract:

A method of creating a structure on an electrode includes exposing an electrode to a solution containing a polymerizable monomer and particles and applying an AC voltage to the electrode so as to induce positive DEP on the particles and to draw the particles toward the electrode. An offset voltage is applied to the electrode (which can be DC or AC) to form an electrically conductive polymer thereon from the polymerizable monomer, wherein the particles are entrapped on or within the polymer.