Vipul V Mehta

US Patent:

20140061902, Mar 6, 2014

Filed:

Aug 31, 2012

Appl. No.:

13/601788

Inventors:

Suriyakala Ramalingam - Chandler AZ, US
Rajen S. Sidhu - Chandler AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Sivakumar Nagarajan - Chandler AZ, US
Wei Tan - Chandler AZ, US
Sandeep Razdan - Chandler AZ, US
Vipul V. Mehta - Chandler AZ, US

International Classification:

H01L 23/498
H01L 21/28
H01L 21/50
H01L 23/48

US Classification:

257738, 257741, 438612, 438107, 257777, 257E2301, 257E23069, 257E21158, 257E21499

Abstract:

Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

US Patent:

20220196937, Jun 23, 2022

Filed:

Dec 23, 2020

Appl. No.:

17/132851

Inventors:

- Santa Clara CA, US
Jingyi HUANG - Chandler AZ, US
Yiqun BAI - Chandler AZ, US
Ziyin LIN - Chandler AZ, US
Vipul MEHTA - Chandler AZ, US
Joseph VAN NAUSDLE - Chandler AZ, US

International Classification:

G02B 6/42

Abstract:

Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

US Patent:

20210391232, Dec 16, 2021

Filed:

Aug 27, 2021

Appl. No.:

17/459993

Inventors:

- Santa Clara CA, US
Kyu Oh Lee - Chandler AZ, US
Siddharth K. Alur - Chandler AZ, US
Wei-Lun K. Jen - Chandler AZ, US
Vipul V. Mehta - Chandler AZ, US
Ashish Dhall - Chandler AZ, US
Sri Chaitra J. Chavali - Chandler AZ, US
Rahul N. Manepalli - Chandler AZ, US
Amruthavalli P. Alur - Tempe AZ, US
Sai Vadlamani - Chandler AZ, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 23/31
H01L 21/48
H01L 21/56
H01L 23/538
H01L 23/00
H01L 25/065
H01L 23/532
H01L 23/498

Abstract:

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

US Patent:

20210272878, Sep 2, 2021

Filed:

Feb 28, 2020

Appl. No.:

16/805392

Inventors:

- Santa Clara CA, US
Vipul Mehta - Chandler AZ, US
John Decker - Tempe AZ, US
Ziyin Lin - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/433
H01L 23/31
H01L 25/065
H01L 25/00
H01L 21/56

Abstract:

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

US Patent:

20210249322, Aug 12, 2021

Filed:

Feb 11, 2020

Appl. No.:

16/788186

Inventors:

- Santa Clara CA, US
Vipul Mehta - Chandler AZ, US
Wei Li - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Xavier Brun - Hillsboro OR, US
Yang Guo - Chandler AZ, US
Soud Choudhury - Chandler AZ, US
Shan Zhong - Chandler AZ, US
Christopher Rumer - Chander AZ, US
Nai-Yuan Liu - Chandler AZ, US
Ifeanyi Okafor - Chandler AZ, US
Hsin-Wei Wang - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/31
H01L 23/367
H01L 23/00

Abstract:

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

US Patent:

20210111088, Apr 15, 2021

Filed:

Dec 29, 2016

Appl. No.:

16/464547

Inventors:

- Santa Clara CA, US
Kyu Oh Lee - Chandler AZ, US
Siddharth K. Alur - Chandler AZ, US
Wei-Lun K. Jen - Chandler AZ, US
Vipul V. Mehta - Chandler AZ, US
Ashish Dhall - Chandler AZ, US
Sri Chaitra J. Chavali - Chandler AZ, US
Rahul N. Manepalli - Chandler AZ, US
Amruthavalli P. Alur - Tempe AZ, US
Sai Vadlamani - Chandler AZ, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 23/31
H01L 25/065
H01L 23/00
H01L 23/538
H01L 21/48
H01L 21/56

Abstract:

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

US Patent:

20210066152, Mar 4, 2021

Filed:

Aug 30, 2019

Appl. No.:

16/557891

Inventors:

- Santa Clara CA, US
Elizabeth NOFEN - Phoenix AZ, US
Vipul MEHTA - Chandler AZ, US
Taylor GAINES - Chandler AZ, US

International Classification:

H01L 23/31
H01L 21/56
H01L 21/67
H01L 23/373
H01L 23/367

Abstract:

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

US Patent:

20210066162, Mar 4, 2021

Filed:

Aug 30, 2019

Appl. No.:

16/557896

Inventors:

- Santa Clara CA, US
Nicholas S. HAEHN - Scottsdale AZ, US
Edvin CETEGEN - Chandler AZ, US
Nicholas NEAL - Scottsdale AZ, US
Jacob VEHONSKY - Gilbert AZ, US
Steve S. CHO - Chandler AZ, US
Rahul JAIN - Gilbert AZ, US
Antariksh Rao Pratap SINGH - Gilbert AZ, US
Tarek A. IBRAHIM - Mesa AZ, US
Thomas HEATON - Mesa AZ, US
Vipul MEHTA - Chandler AZ, US

International Classification:

H01L 23/42
H01L 23/00

Abstract:

A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.