Virendra S Negi

US Patent:

43097537, Jan 5, 1982

Filed:

Jan 3, 1979

Appl. No.:

6/000734

Inventors:

Virendra S. Negi - Pepperell MA
Arthur Peters - Sudbury MA

Assignee:

Honeywell Information System Inc. - Waltham MA

International Classification:

G06F 926

US Classification:

364200

Abstract:

A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.

US Patent:

44234830, Dec 27, 1983

Filed:

Dec 24, 1980

Appl. No.:

6/220219

Inventors:

Steven A. Tague - Billerica MA
Virendra S. Negi - Pepperell MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 750

US Classification:

364200

Abstract:

A data processing system includes a commercial instruction processor (CIP) for executing decimal arithmetic instructions. The operands processed by the CIP include packed decimal and string decimal operands. The decimal arithmetic instruction includes descriptors for describing the characteristics of the operands. A register coupled to an arithmetic logic unit stores double words of the operands which are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory. The read only memory output write signals select the decimal digit, byte or double word positions of the register for writing.

US Patent:

42246687, Sep 23, 1980

Filed:

Jan 3, 1979

Appl. No.:

6/000864

Inventors:

Arthur Peters - Sudbury MA
Virendra S. Negi - Pepperell MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 920

US Classification:

364200

Abstract:

A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.

US Patent:

43843409, May 17, 1983

Filed:

Dec 24, 1980

Appl. No.:

6/220220

Inventors:

Steven A. Tague - Billerica MA
Virendra S. Negi - Pepperell MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 750
G06F 752

US Classification:

364736

Abstract:

A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from a descriptor word of the instruction, and signals indicating the present decimal digit position being processed to generate signals indicating next decimal digit position to be processed.

US Patent:

43228461, Mar 30, 1982

Filed:

Apr 15, 1980

Appl. No.:

6/140621

Inventors:

Elmer W. Carroll - Wilmington MA
Virendra S. Negi - Pepperell MA
Arthur Peters - Sudbury MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1100

US Classification:

371 16

Abstract:

In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.

US Patent:

40500977, Sep 20, 1977

Filed:

Sep 27, 1976

Appl. No.:

5/727194

Inventors:

Ming T. Miu - Chelmsford MA
Virendra S. Negi - Pepperell MA
Richard A. Lemay - Bolton MA

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

G06F 104

US Classification:

364200

Abstract:

Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

US Patent:

44478704, May 8, 1984

Filed:

Apr 3, 1981

Appl. No.:

6/250823

Inventors:

Steven A. Tague - Billerica MA
Virendra S. Negi - Pepperell MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 104

US Classification:

364200

Abstract:

A microprogrammed commercial instruction processor in a data processing system includes a bank of switches coupled to a multitapped delay line for selecting delay line signals for setting the basic clock timing. Another of the switches when activated conditions the commercial instruction processor so that when it is reset a special clock setting firmware loop is entered. The loop provides an uninterrupted succession of clock pulses which allows one to adjust the basic clock timing within specification.

US Patent:

42187397, Aug 19, 1980

Filed:

Oct 28, 1976

Appl. No.:

5/736657

Inventors:

Virendra S. Negi - Pepperell MA
Ming T. Miu - Chelmsford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 918

US Classification:

364200

Abstract:

Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.