Vivek J Garg
age ~54
from Round Rock, TX
Vivek Garg Phones & Addresses
- 4415 Pasada Ln, Round Rock, TX 78681
- 432 Lakeview Dr, Newark, DE 19711
- 257 Oxburough Dr, Folsom, CA 95630 • 9163551676
- 3500 Data Dr, Rancho Cordova, CA 95670
- Atlanta, GA
- Sacramento, CA
- 257 Oxburough Dr, Folsom, CA 95630
Amazon
CM to PM: Narendra Modi
view sourceTelling the story of Narendra Modi and the state of Gujarat is not easy because so many things are fiercely contested. It is not wrong to call him a man of his time. Modi over the last more than one decade was able to brave through the challenges from all corners political rivals in Congress and oth...
Author
Vivek Garg, Nirendra Dev
Binding
Hardcover
Publisher
Manas Publications
ISBN #
8170494680
EAN Code
9788170494683
ISBN #
1
Master Plan for Delhi 2021
view sourceAuthor
Vivek Garg
Binding
Hardcover
Publisher
Manas Publications
ISBN #
8170493358
EAN Code
9788170493358
ISBN #
4
2G Bomb: RTIs Shook North Block
view sourceThe C&AG report tells that the 2G spectrum scam cost the country approximately Rs 1,76,645 crores. The amount involved in 2G spectrum scam is so huge that one cannot imagine that this scam did materialize without the involvement of the top political masters. How come nobody in the Prime Minister's O...
Author
Vivek Garg
Binding
Hardcover
Pages
400
Publisher
Manas Publications
ISBN #
8170494214
EAN Code
9788170494218
ISBN #
5
Manmohanomics: Journey to South Block - Life of an Indian Prime Minister
view sourceThis book charts the career and persona of Dr. Manmohan Sigh,since his humble beginning in the Gah village, now in Pakistan, to his becoming the Prime Minister of India, the biggest democracy in the world. Singh is not the run-of-the-mill Indian politician. Rather, he is the average Indian at heart....
Author
Vivek Garg, Ravish Mishra
Binding
Hardcover
Pages
256
Publisher
Manas Publications
ISBN #
8170492114
EAN Code
9788170492115
ISBN #
3
PMO to Delhi Secretariat: RITIs Expose Common-Wealth Scam
view sourceThe Commonwealth Games (CWG) 2010 scam is a real shocker. Like 2G spectrum scam, it is one of the biggest scams India has witnessed in the recent past. The most galling aspect of this scam is that nobody in the Prime Minister's Office (PMO), Ministry of Sports and Youth Affairs, and the Delhi Govern...
Author
Vivek Garg
Binding
Hardcover
Pages
496
Publisher
Manas Publications
ISBN #
8170494362
EAN Code
9788170494362
ISBN #
2
Master Plan for Delhi 2021 (MPD - 2021) (As Notified on 7.2.2007 Vide S.O. No. 141. Published in Gazette of India. Extraordinary. Part II. Section-3. Sub-Section (ii)).jpg
view source8170493358|9788170493358. Master Plan for Delhi 2021 (MPD - 2021) (As Notified on 7.2.2007 Vide S.O. No. 141. Published in Gazette of India. Extraordinary. Part II. Section-3. Sub-Section (ii)) published in the year 2007 was published by Manas Publications. The author of this book is Vivek Kr. Garg....
Author
Vivek Kr. Garg
Binding
Paperback
ISBN #
6
Us Patents
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Opportunistic Sharing Of Graphics Resources To Enhance Cpu Performance In An Integrated Microprocessor
view source -
US Patent:6842180, Jan 11, 2005
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Filed:Sep 20, 2000
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Appl. No.:09/665923
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Inventors:Subramaniam Maiyuran - Gold River CA, US
Vivek Garg - Rancho Cordova CA, US
Jagannath Keshava - Folsom CA, US
Salvador Palanca - Folsom CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 15167
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US Classification:345541, 711122, 711119
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Abstract:An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit. The method also shares an available memory component as a pre-fetch buffer and another available memory component as a victim cache.
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Method And Apparatus For Shared Cache Coherency For A Chip Multiprocessor Or Multiprocessor System
view source -
US Patent:6976131, Dec 13, 2005
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Filed:Aug 23, 2002
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Appl. No.:10/226478
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Inventors:Vladimir Pentkovski - Folsom CA, US
Vivek Garg - Folsom CA, US
Narayanan S. Iyer - Folsom CA, US
Jagannath Keshava - Folsom CA, US -
Assignee:Intel Corporation - Santa Clara CA
-
International Classification:G06F012/00
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US Classification:711146, 711141, 711130, 711156
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Abstract:A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
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Cache Sharing For A Chip Multiprocessor Or Multiprocessing System
view source -
US Patent:7076609, Jul 11, 2006
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Filed:Sep 20, 2002
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Appl. No.:10/251096
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Inventors:Vivek Garg - Folsom CA, US
Jagannath Keshava - Folsom CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 12/00
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US Classification:711120, 711 3, 711133, 711148
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Abstract:Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow sharing between caches that are associated with individual processor cores.
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Store Performance In Strongly-Ordered Microprocessor Architecture
view source -
US Patent:7484045, Jan 27, 2009
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Filed:Mar 30, 2004
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Appl. No.:10/813942
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Inventors:Ling Cen - Austin TX, US
Vivek Garg - Folsom CA, US
Deep Buch - Folsom CA, US
David Zhao - Pinole CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 12/08
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US Classification:711145, 711152
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Abstract:A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.
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Avoiding Deadlocks In A Multiprocessor System
view source -
US Patent:7600080, Oct 6, 2009
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Filed:Sep 22, 2006
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Appl. No.:11/525585
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Inventors:Binata Bhattacharyya - Bangalore, IN
Chandra P. Joshi - Bangalore, IN
Chung-Chi Wang - Sunnyvale CA, US
Liang Yin - San Jose CA, US
Vivek Garg - Folsom CA, US
Phanindra K. Mannava - Folsom CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 12/00
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US Classification:711143, 711118, 711119, 711128, 711135, 711141, 711147, 711148
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Abstract:In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.
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Uncore Thermal Management
view source -
US Patent:7694161, Apr 6, 2010
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Filed:Jun 30, 2006
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Appl. No.:11/479408
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Inventors:Deep Buch - Folsom CA, US
Vivek Garg - Folsom CA, US
Subramaniam Maiyuran - Goldriver CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 1/32
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US Classification:713324, 713323, 714 48
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Abstract:A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
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Dynamic Allocation Of Home Coherency Engine Tracker Resources In Link Based Computing System
view source -
US Patent:7831776, Nov 9, 2010
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Filed:Oct 12, 2006
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Appl. No.:11/580738
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Inventors:Phanindra K Mannava - Folsom CA, US
Vivek Garg - Folsom CA, US
Stan Domen - Roseville CA, US -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 12/00
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US Classification:711144
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Abstract:A home agent allocates trackers to each of a plurality of caching agents, monitors each caching agent's usage of the allocated trackers, and determines whether a caching agent under-utilizes or over-utilizes them. In the case of under-utilization, the home agent retrieves at least one tracker from the allocation to the caching agent. In the case of over-utilization, the home agent allocates more trackers to the caching agent.
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Synchronizing Control And Data Paths Traversed By A Data Transaction
view source -
US Patent:7836229, Nov 16, 2010
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Filed:Jun 23, 2006
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Appl. No.:11/474140
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Inventors:Bipin P. Singh - Bangalore, IN
Vivek Garg - Folsom CA, US
Binata Bhattacharyya - Bangalore, IN -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:G06F 3/00
G06F 5/00 -
US Classification:710 52
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Abstract:In one embodiment, the present invention includes a method for determining if control and data portions of a data transaction are ready to be sent from an interface coupled to a processor core. If so, the data portion may be sent from an entry of a data buffer of the interface, and the entry deallocated. Furthermore, a value corresponding to the deallocated entry may be written in multiple buffers of the interface. In this way, independent paths of the interface may be synchronized. Other embodiments are described and claimed.
Resumes
Senior Qa Analyst At Electronic Transaction Consultants Corporation (Etcc)
view sourcePosition:
Senior QA Analyst at Electronic Transaction Consultants Corporation (ETCC)
Location:
Richardson, Texas
Industry:
Information Technology and Services
Work:
Electronic Transaction Consultants Corporation (ETCC) - Richardson Texas since Aug 2012
Senior QA Analyst
CVS Caremark Corporation - Richardson TX Apr 2011 - Jul 2012
Test Lead
What a Burger , San Antonio Texas Dec 2010 - Mar 2011
Test Lead
Walmart, bentonville, Arkansas Jul 2010 - Nov 2010
GLMS, Test Lead
Mckesson Provider Technologies, Atlanta, GA Aug 2009 - Jul 2010
Ovation, Senior QA Analyst
Senior QA Analyst
CVS Caremark Corporation - Richardson TX Apr 2011 - Jul 2012
Test Lead
What a Burger , San Antonio Texas Dec 2010 - Mar 2011
Test Lead
Walmart, bentonville, Arkansas Jul 2010 - Nov 2010
GLMS, Test Lead
Mckesson Provider Technologies, Atlanta, GA Aug 2009 - Jul 2010
Ovation, Senior QA Analyst
Education:
PDA College of Engineering
BE, Electrical and Electronics Engineering
BE, Electrical and Electronics Engineering
Skills:
Management
SharePoint
Quality Center
Testing
Quality Assurance
User Acceptance Testing
Training
Leadership
Integration
Unix
Test Cases
Test Planning
Requirements Analysis
Regression Testing
SDLC
SharePoint
Quality Center
Testing
Quality Assurance
User Acceptance Testing
Training
Leadership
Integration
Unix
Test Cases
Test Planning
Requirements Analysis
Regression Testing
SDLC
Interests:
Reading , Travel, Meeting new people,New Technology.
Honor & Awards:
Got scholarship in class 10th.
AT&T Sensational award for outstanding work.
Several client appreciation mails for my outstanding work in various projects.
Vivek Garg
view sourceLocation:
United States
Medicine Doctors
Vivek K. Garg
view sourceSpecialties:
Internal Medicine
Work:
One Medical Group
408 W 14 St STE 201, New York, NY 10014
2125300639 (phone), 2128674353 (fax)
408 W 14 St STE 201, New York, NY 10014
2125300639 (phone), 2128674353 (fax)
Education:
Medical School
Harvard Medical School
Graduated: 2009
Harvard Medical School
Graduated: 2009
Procedures:
Vaccine Administration
Conditions:
Acute Bronchitis
Acute Upper Respiratory Tract Infections
Anxiety Phobic Disorders
Attention Deficit Disorder (ADD)
Erectile Dysfunction (ED)
Acute Upper Respiratory Tract Infections
Anxiety Phobic Disorders
Attention Deficit Disorder (ADD)
Erectile Dysfunction (ED)
Languages:
English
Description:
Dr. Garg graduated from the Harvard Medical School in 2009. He works in New York, NY and specializes in Internal Medicine.
Isbn (Books And Publications)
Manmohanomics, Journey to South Block: Life of an Indian Prime Minister
view sourceAuthor
Vivek Garg
ISBN #
8170492114
Mylife
Vivek Garg
view sourceLocality:
Salt Lake City, UT
Vivek Garg
view sourceLocality:
Charlotte, NC
Vivek Garg
view sourceLocality:
Richardson, TX
Vivek Garg
view sourceLocality:
Coral Gables, FL
Vivek Garg
view sourceLocality:
Round Rock, TX
Vivek Kumar Garg
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Vivek Garg
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Vivek Garg
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Vivek Garg
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Vivek Garg
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Vivek Garg
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Vivek Garg
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Vivek Garg
view sourceYoutube
Plaxo
Vivek Garg
view sourceDubai
Vivek Garg
view sourcedaffodil
Classmates
Baptist Academy, Indianap...
view sourceGraduates:
Dimple Garg (2000-2004),
Hiral Vyas (2001-2005),
Oni Oluwaseyi (2006-2010),
Vivek Garg (2004-2008),
Abiola Doherty (1998-2002),
Naveen Battini (2003-2007)
Hiral Vyas (2001-2005),
Oni Oluwaseyi (2006-2010),
Vivek Garg (2004-2008),
Abiola Doherty (1998-2002),
Naveen Battini (2003-2007)
Myspace
Flickr
Googleplus
Vivek Garg
Work:
Broadcom - Intern (2013)
Education:
Columbia University - Computer science, Indian Institute of Technology Madras - Computer Science & Engg., National Institute of Technology, Hamirpur - Computer Science & Engg.
Vivek Garg
Work:
Bharat National Public School - Teaching
Education:
Hansraj college - M.Sc. Maths, University of Delhi
Vivek Garg
Education:
DCE-DTU - EEE, DPS VASANT KUNJ, Amity International School , Sec-43 GGN
Vivek Garg
Education:
Kendriya Vidyalaya
About:
Bachelor's Technology in Computers.
Tagline:
I am a constant learner
Vivek Garg
Work:
Public Health Engineering Department, Haryana - Programmer
Education:
DOEACC, Changigarh - 'B' - Level, S. A. Jain College, Ambala City - B. Sc.
Vivek Garg
Education:
Yale School of Management, Indian Institute of Technology Roorkee - Civil Engineering
Vivek Garg
Work:
Intel Corporation (2006-2012)
Education:
Columbia University - Computer Engineering
Vivek Garg
Work:
Patho logy
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