Vivek V Gupta

Address:

1000 Escalon Ave APT N1112, Sunnyvale, CA 94085

VIN:

4JGCB65E17A056253

Make:

MERCEDES-BENZ

Model:

R-CLASS

Year:

2007

US Patent:

6888795, May 3, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/134012

Inventors:

Vivek Gupta - Palo Alto CA, US
Sumit Sanyal - Palo Alto CA, US
Xiangzhong Zeng - San Jose CA, US
Stephen J. Sifferman - Santa Clara CA, US
Leah J. Fera - San Jose CA, US
Christopher R. Uhlik - Danville CA, US

Assignee:

Durham Logistics LLC - Las Vegas NV

International Classification:

G01R031/08

US Classification:

370230, 370329

Abstract:

Allocating resources in a circuit switched data network, comprising receiving a request for a resource from a device coupled to the circuit switched data network and granting the resource to the requesting device if the resource is available. If the resource is not available, then examining the instantaneous quantity of data to be transmitted by the requesting device; the rate of change in the instantaneous quantity of data to be transmitted by the requesting device; and the time of utilization of the resource by the requesting device, and granting the resource to the requesting device based on the examination of the three factors.

US Patent:

7080271, Jul 18, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367566

Inventors:

James P. Kardach - Saratoga CA, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US
Vivek Gupta - Portland OR, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Flemming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/32

US Classification:

713323, 710 15

Abstract:

A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.

US Patent:

7114090, Sep 26, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367240

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713323, 713300, 713322, 713324

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7406610, Jul 29, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/262212

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7421597, Sep 2, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/261255

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713322, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7428650, Sep 23, 2008

Filed:

May 15, 2006

Appl. No.:

11/435264

Inventors:

James P. Kardach - Saratoga CA, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US
Vivek Gupta - Portland OR, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Flemming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00
G06F 3/00

US Classification:

713323, 710 15

Abstract:

A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

US Patent:

7554913, Jun 30, 2009

Filed:

Mar 25, 2005

Appl. No.:

11/089958

Inventors:

Vivek Gupta - Palo Alto CA, US
Sumit Sanyal - Palo Alto CA, US
Xiangzhong Zeng - San Jose CA, US
Stephen J. Sifferman - Santa Clara CA, US
Leah J. Fera - San Jose CA, US
Christopher R. Uhlik - Danville CA, US

International Classification:

G01R 31/08

US Classification:

370234, 370252, 370329

Abstract:

Allocating resources in a circuit switched data network, comprising receiving a request for a resource from a device coupled to the circuit switched data network and granting the resource to the requesting device if the resource is available. If the resource is not available, then examining the instantaneous quantity of data to be transmitted by the requesting device; the rate of change in the instantaneous quantity of data to be transmitted by the requesting device; and the time of utilization of the resource by the requesting device, and granting the resource to the requesting device based on the examination of the three factors.

US Patent:

7734607, Jun 8, 2010

Filed:

Feb 1, 2006

Appl. No.:

11/346609

Inventors:

Georges Grinstein - Ashby MA, US
Alexander Gee - Lowell MA, US
Urska Cvek - Shreveport LA, US
Howard Goodell - Salem NH, US
Hongli Li - Westborough MA, US
Min Yu - North Chelmsford MA, US
Jianping Zhou - Acton MA, US
Vivek Gupta - Littleton MA, US
Mary Beth Smrtic - Westford MA, US
Christine Lawrence - Waltham MA, US
Chih-Hung Chiang - North Chelmsford MA, US

Assignee:

University of Massachusetts - Boston MA

International Classification:

G06F 17/30

US Classification:

707705, 719328, 707E17065, 707E17067, 715848

Abstract:

The invention relates to a framework system and methods for connecting a plurality of tools. The system comprises a plug-in mechanism configured to dynamically load the plurality of tools, a data pool having storage space configured to store data sets associated with the plurality of tools, a linking mechanism configured to establish communications links between the loaded plurality of tools to enable coordinated operation of the loaded plurality of tools, a session component configured to record the process history of the operations of the loaded plurality of tool and the system states corresponding to the process history of the operations and an annotation module configured to associate user-provided data corresponding to one or more of the stored data sets.