Vivek I Gupta

US Patent:

6473793, Oct 29, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/233343

Inventors:

Douglas M. Dillon - Gaithersburg MD
Vivek Gupta - Gaithersburg MD

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

G06F 1516

US Classification:

709223, 370235, 370352, 370401

Abstract:

A hybrid gateway includes functionality that allows bandwidth on a network (such as a satellite link) to be dynamically allocated and enforced. The hybrid gateway compares the thresholds defined for a requesting terminals level of service and its measured running average data throughput to determine if the requesting terminals bandwidth should be reduced (throttled). The hybrid gateway intercepts requests made by the requesting terminals and, if necessary, reduces the advertized window size of requests made by the requesting terminal, thereby reducing the transmission speed of the link and therefore the bandwidth of the link.

US Patent:

6888795, May 3, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/134012

Inventors:

Vivek Gupta - Palo Alto CA, US
Sumit Sanyal - Palo Alto CA, US
Xiangzhong Zeng - San Jose CA, US
Stephen J. Sifferman - Santa Clara CA, US
Leah J. Fera - San Jose CA, US
Christopher R. Uhlik - Danville CA, US

Assignee:

Durham Logistics LLC - Las Vegas NV

International Classification:

G01R031/08

US Classification:

370230, 370329

Abstract:

Allocating resources in a circuit switched data network, comprising receiving a request for a resource from a device coupled to the circuit switched data network and granting the resource to the requesting device if the resource is available. If the resource is not available, then examining the instantaneous quantity of data to be transmitted by the requesting device; the rate of change in the instantaneous quantity of data to be transmitted by the requesting device; and the time of utilization of the resource by the requesting device, and granting the resource to the requesting device based on the examination of the three factors.

US Patent:

6931512, Aug 16, 2005

Filed:

Nov 13, 2001

Appl. No.:

10/054681

Inventors:

Douglas M. Dillon - Gaithersburg MD, US
Vivek Gupta - Gaithersburg MD, US

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

G06F015/173
H04N007/20
H04L012/66
H04L012/64

US Classification:

712 29, 709233, 709235, 725 81, 725109, 370233

Abstract:

A requesting terminal includes an interface that allows a user to select whether data downloaded from a network (such as the Internet) is transmitted to the requesting terminal via a high-speed link, such as a satellite link, or a lower speed link, such as a terrestrial link. Preferably, the terrestrial link (which may comprise a conventional dial-up Internet connection) is a two-way link, wherein the requesting terminal transmits data requests to the network via the terrestrial link. The data requests generated by the requesting terminal are modified to designate whether the requested data should be downloaded from the network via the terrestrial link or the satellite link. The terrestrial link may also be automatically selected for certain applications.

US Patent:

7080271, Jul 18, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367566

Inventors:

James P. Kardach - Saratoga CA, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US
Vivek Gupta - Portland OR, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Flemming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/32

US Classification:

713323, 710 15

Abstract:

A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.

US Patent:

7114090, Sep 26, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367240

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713323, 713300, 713322, 713324

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7406610, Jul 29, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/262212

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7421597, Sep 2, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/261255

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713322, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7428650, Sep 23, 2008

Filed:

May 15, 2006

Appl. No.:

11/435264

Inventors:

James P. Kardach - Saratoga CA, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US
Vivek Gupta - Portland OR, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Flemming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00
G06F 3/00

US Classification:

713323, 710 15

Abstract:

A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.