Vivek G Gupta

US Patent:

6888795, May 3, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/134012

Inventors:

Vivek Gupta - Palo Alto CA, US
Sumit Sanyal - Palo Alto CA, US
Xiangzhong Zeng - San Jose CA, US
Stephen J. Sifferman - Santa Clara CA, US
Leah J. Fera - San Jose CA, US
Christopher R. Uhlik - Danville CA, US

Assignee:

Durham Logistics LLC - Las Vegas NV

International Classification:

G01R031/08

US Classification:

370230, 370329

Abstract:

Allocating resources in a circuit switched data network, comprising receiving a request for a resource from a device coupled to the circuit switched data network and granting the resource to the requesting device if the resource is available. If the resource is not available, then examining the instantaneous quantity of data to be transmitted by the requesting device; the rate of change in the instantaneous quantity of data to be transmitted by the requesting device; and the time of utilization of the resource by the requesting device, and granting the resource to the requesting device based on the examination of the three factors.

US Patent:

7010656, Mar 7, 2006

Filed:

Jan 28, 2003

Appl. No.:

10/353427

Inventors:

Vivek G. Gupta - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711165, 711 5, 711154, 711170, 711202, 711203, 711206, 711209, 713324

Abstract:

In some embodiments, an electronic device includes a processor, a physical memory coupled to the processor, and a storage medium coupled to the processor. The storage medium may store instructions which when executed by the processor cause the processor to: survey at least a portion of the physical memory, determine an amount of free memory space and used memory space based on the survey of the physical memory, determine if a consolidation of used memory space should be performed, and, if so determined, consolidate the used memory space, and reduce the power provided to at least a portion of the physical memory following the consolidation of used memory space. Other embodiments are disclosed and claimed.

US Patent:

7080271, Jul 18, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367566

Inventors:

James P. Kardach - Saratoga CA, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US
Vivek Gupta - Portland OR, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Flemming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/32

US Classification:

713323, 710 15

Abstract:

A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.

US Patent:

7114090, Sep 26, 2006

Filed:

Feb 14, 2003

Appl. No.:

10/367240

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713323, 713300, 713322, 713324

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7162279, Jan 9, 2007

Filed:

Dec 20, 2002

Appl. No.:

10/326460

Inventors:

Vivek G. Gupta - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04M 1/00
H01Q 11/12

US Classification:

455574, 4551275, 455522, 713320, 713340

Abstract:

Briefly, in accordance with one embodiment of the invention, a portable communication device includes two processors. A power management controller may be adapted to alter an operational characteristic of the processors. In an alternative embodiment, the power management controller may be further adapted to vary an operational characteristics of one processor while leaving the other processor substantially unchanged.

US Patent:

7373111, May 13, 2008

Filed:

Feb 19, 2004

Appl. No.:

10/782474

Inventors:

Vivek G. Gupta - Portland OR, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04B 7/00

US Classification:

455 413, 455515, 455509, 455 903

Abstract:

An apparatus and a system, as well as a method and article, may operate to reserve access for a source device included in a plurality N of source devices to N−1 logical channels accessible by a set of target devices included in the plurality of source devices by creating a static map, wherein N is a positive integer.

US Patent:

7406610, Jul 29, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/262212

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

US Patent:

7421597, Sep 2, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/261255

Inventors:

James P. Kardach - Saratoga CA, US
Jeffrey L. Huckins - Chandler AZ, US
Kristoffer D. Fleming - Chandler AZ, US
Uma M. Gadamsetty - Chandler AZ, US
Vivek Gupta - Portland OR, US
Brian V. Belmont - Portland OR, US
Muthu K. Kumar - Hillsboro OR, US
Riley W. Jackson - Portland OR, US
Gunner Danneels - Beaverton OR, US
Richard A. Forand - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713322, 713323

Abstract:

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.