Wade D Nelson

US Patent:

43981038, Aug 9, 1983

Filed:

Jun 19, 1981

Appl. No.:

6/275530

Inventors:

Edward Derzawiec - Mesa AZ
Wade H. Nelson - Mesa AZ
Cleon Petty - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1920
H03K 3288

US Classification:

307454

Abstract:

In order to reduce the time it takes on-chip circuitry to generate an internal enabling signal from an external clock signal and an external enabling signal, the external clock signal is applied directly to the non-inverting input of an AB gate. The output of the AB gate and an external enabling signal are provided to first and second inputs of a NOR gate the output of which represents the internal enabling signal which is fed back to the inverting input of the AB gate. Thus, the clock signal propagates through only two stages of delay rather than three as is the case with prior art enabling circuitry.

Address:

8040 E Gail Rd, Scottsdale, AZ 85260

Phone:

4803612136

VIN:

JTHBJ46G872060400

Make:

LEXUS

Model:

ES 350

Year:

2007