Walker E Anderson

US Patent:

6629251, Sep 30, 2003

Filed:

Oct 20, 1999

Appl. No.:

09/420983

Inventors:

Walker Edward Anderson - San Diego CA
Thomas Gordon Palkert - Excelsior MN
Robert S. Tepper - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G06F 112

US Classification:

713401, 713400, 713600, 710 52

Abstract:

An elastic store circuit using a first in/first out buffer (FIFO) to accurately delay and manipulate a waveform using the write (WR) and read (RD) clocks is provided. The FIFO delays data by, first, reading the input data at the WR clock rate. Then, the data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD phase change results from introducing a phase change into the reference clock driving the RD clock synthesizer. A method of introducing precise delays through phase control of the WR and RD clocks is also provided.

US Patent:

6681272, Jan 20, 2004

Filed:

Oct 20, 1999

Appl. No.:

09/420976

Inventors:

Walker Edward Anderson - San Diego CA
Thomas Gordon Palkert - Excelsior MN
Robert S. Tepper - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G06F 1314

US Classification:

710 52, 713400, 713401, 375375, 375372

Abstract:

An elastic store circuit using a first in/first out buffer (FIFO) to accurately control the phase delay in a waveform using the write (WR) and read (RD) clocks is provided. The FIFO reads the input data at the WR clock rate. The data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD clock phase change results from phase-locking the RD clock to a phase offset version of the reference clock. A method of introducing precise delays through phase delay of the RD clock with respect to the reference clock is also provided.