Walter David Braddock

US Patent:

6445015, Sep 3, 2002

Filed:

Aug 11, 2000

Appl. No.:

09/638130

Inventors:

Walter David Braddock - Rochester MN

Assignee:

Osemi, Incorporated - Rochester MN

International Classification:

H01L 31072

US Classification:

257192, 257412, 257406, 257410, 257411

Abstract:

A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor ( ) includes a lower sulfide layer that is a mixture of Ga S, Ga S , and other gallium sulfide compounds ( ), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface ( ) of a III-V compound semiconductor wafer structure ( ). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer ( ) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure ( ). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer. A refractory metal gate electrode layer ( ) is positioned on upper surface ( ) of the second insulating sulfide layer.

US Patent:

6573528, Jun 3, 2003

Filed:

Oct 12, 2001

Appl. No.:

09/976907

Inventors:

Walter David Braddock - Rochester MN 55906-3714

International Classification:

H01L 310328

US Classification:

257 14, 257 12, 257 15, 257 16, 257 17, 257 18, 257 22, 257 94, 257 96, 257 97, 257103, 257183, 257199, 257200, 257472, 257631

Abstract:

This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation. The diode structure comprises a semiconductor substrate, a verification structure consisting of alternating layers of binary compound semiconductors that exist in crystalline form on said substrate, a doped contact layer with sufficient doping and thickness to provide for the formation of electrical contact with ohmic behavior, a barrier structure consisting of some combination of multiple heterojunctions and alternating layers that may be periodic in nature or of a chirped superlattice nature in said barrier, and a doped contact layer that is of the proper thickness and doping to allow the formation of a sufficient electrical contact with ohmic or partly resistive nature as necessary for the required contact.

US Patent:

6670651, Dec 30, 2003

Filed:

Aug 12, 2000

Appl. No.:

09/638384

Inventors:

Walter David Braddock - Rochester MN

Assignee:

Osemi, Inc. - Rochester MN

International Classification:

H01L 31072

US Classification:

257192, 257406, 257410, 257411, 257412

Abstract:

A self-aligned enhancement mode metal-sulfide-oxide-compound semiconductor field effect transistor ( ) includes a lower sulfide layer that is a mixture of Ga S, Ga S , and other gallium sulfide compounds ( ), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface ( ) of a III-V compound semiconductor wafer structure ( ). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide-oxide gate insulating structure. The gallium sulfide-oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer ( ) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure ( ). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer. The insulating layer deposited upon the gallium sulphur layer is composed of gallium oxygen and at least one rare earth elemental layer deposited so that it is highly insulating in nature.

US Patent:

6989556, Jan 24, 2006

Filed:

Jun 6, 2002

Appl. No.:

10/163506

Inventors:

Walter David Braddock - Rochester MN, US

Assignee:

Osemi, Inc. - Rochester MN

International Classification:

H01L 29/94
H01L 21/336

US Classification:

257192, 257289, 257410, 257411, 257412, 438285, 438287, 438590, 438591

Abstract:

A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor () includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds () positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer () meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination. A refractory metal gate electrode layer () is positioned on upper surface () of the second insulating layer.

US Patent:

7187045, Mar 6, 2007

Filed:

Jul 16, 2002

Appl. No.:

10/198705

Inventors:

Walter David Braddock - Rochester MN, US

Assignee:

OSEMI, Inc. - Cannon Falls MN

International Classification:

H01L 29/76
H01L 21/336

US Classification:

257411, 257410, 438216, 438261, 438287

Abstract:

A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.

US Patent:

20060076630, Apr 13, 2006

Filed:

Feb 9, 2005

Appl. No.:

11/052889

Inventors:

Walter Braddock - Rochester MN, US

International Classification:

H01L 29/94

US Classification:

257412000

Abstract:

A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor () includes a lower oxide layer that is a mixture of GaO, GaO, and other gallium oxide compounds (), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface () of a III-V compound semiconductor wafer structure (). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer () meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer () is positioned on upper surface () of the second insulating oxide layer. The refractory metal is stable on the second insulating oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts () are positioned on the source and drain areas () of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

US Patent:

20070138506, Jun 21, 2007

Filed:

Nov 17, 2004

Appl. No.:

10/579537

Inventors:

Walter Braddock - Rochester MN, US

International Classification:

H01L 31/00
H01L 29/739

US Classification:

257192000, 257201000, 257194000

Abstract:

A self-aligned enhancement mode or depletion mode nitride based metal-oxide-compound semiconductor field effect transistor () includes a gate insulating structure comprised of a first oxide layer that in comprised of gallium oxides or indium oxides compounds () positioned immediately on top of the nitride compound semiconductor structure, and a second insulating layer comprised of either (a) oxygen and rare earth elements, (b) gallium oxygen and rare earth elements, or (c) gallium+indium and rare earth elements positioned immediately on top of said first layer. Together the lower indium oxide or gallium oxide layer and the second insulating layer form a epitaxial oxide gate insulating structure. The gate insulating structure and underlying compound semiconductor layer () meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure () that is based on the nitride family of compound semiconductors. The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination. A refractory metal gate electrode layer () is positioned on upper surface () of the second insulating layer. The refractory metal is stable on the second insulating layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts () are positioned on the source and drain areas () of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form an integrated circuit structure. Finally, NMOS and PMOS nitride based devices are positioned in proximity to for a complementary metal oxide semiconductor integrated circuit in nitride based compound semiconductors.

US Patent:

20080157073, Jul 3, 2008

Filed:

Dec 29, 2006

Appl. No.:

11/618212

Inventors:

Walter David Braddock - Rochester MN, US

International Classification:

H01L 29/78
H01L 21/34

US Classification:

257 43, 438104, 257E29255, 257E2146

Abstract:

A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor () includes a lower oxide layer that is a mixture of GaO, GaO, and other gallium oxide compounds (), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface () of a III-V compound semiconductor wafer structure (). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer () meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor sure from the second insulating oxide layer. A refractory mal gate electrode layer () is positioned on upper surface () of the second insulating oxide layer. The refractory metal is stable on the second insulating oxide layer at elevated temperate. Self-aligned source and drain areas, and source and drain contacts () are positioned on the source and drain areas () of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers at insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.