Walter R Lockwood

US Patent:

7770067, Aug 3, 2010

Filed:

Dec 1, 2008

Appl. No.:

12/325272

Inventors:

Walter R. Lockwood - Round Rock TX, US
Ryan J. Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth L. Wright - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 30

Abstract:

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

US Patent:

20070101194, May 3, 2007

Filed:

Oct 27, 2005

Appl. No.:

11/260562

Inventors:

Walter Lockwood - Round Rock TX, US
Ryan Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth Wright - Austin US, US

International Classification:

G06F 11/00

US Classification:

714030000

Abstract:

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

US Patent:

20090006916, Jan 1, 2009

Filed:

Sep 9, 2008

Appl. No.:

12/207496

Inventors:

Walter R. Lockwood - Round Rock TX, US
Ryan J. Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth L. Wright - Austin TX, US

International Classification:

G06F 11/26

US Classification:

714733, 714E11159

Abstract:

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.