Wayne R Buzby

US Patent:

6480973, Nov 12, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409456

Inventors:

William A. Shelly - Phoenix AZ
David A. Egolf - Glendale AZ
Wayne R. Buzby - Phoenix AZ

Assignee:

Bull Information Systems Inc. - Billerica MA

International Classification:

G06F 1100

US Classification:

714 30, 711131

Abstract:

In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This âunfairâ memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by âbalkingâ or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

US Patent:

6484272, Nov 19, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409811

Inventors:

David A. Egolf - Glendale AZ
William A. Shelly - Phoenix AZ
Wayne R. Buzby - Phoenix AZ

Assignee:

Bull HN Information Systems, Inc. - Billerica MA

International Classification:

G06F 100

US Classification:

714 30, 714738, 714742, 714 47, 711167, 711168

Abstract:

In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This âunfairâ memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by âbalkingâ or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

US Patent:

6687845, Feb 3, 2004

Filed:

Dec 20, 2000

Appl. No.:

09/742456

Inventors:

Wayne R. Buzby - Phoenix AZ
Sidney L. Andress - Glendale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1324

US Classification:

714 2, 714 34, 714 48, 710 48, 710260, 710269

Abstract:

A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

US Patent:

6697959, Feb 24, 2004

Filed:

Dec 20, 2000

Appl. No.:

09/742457

Inventors:

Sidney L. Andress - Glendale AZ
Wayne R. Buzby - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1107

US Classification:

714 10, 714 2, 710 48, 710 50, 710260, 710269

Abstract:

A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

US Patent:

6760811, Jul 6, 2004

Filed:

Aug 15, 2002

Appl. No.:

10/219644

Inventors:

Wayne R. Buzby - Phoenix AZ
Charles P. Ryan - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1200

US Classification:

711130, 711118, 711119, 711120, 711121, 711122, 711147

Abstract:

In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a âset gate control flagâ command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor. Optionally, the processor so acquiring ownership broadcasts a âreset gate control flagâ command to all processors when it has acquired ownership of the gate control word.

US Patent:

6779132, Aug 17, 2004

Filed:

Aug 31, 2001

Appl. No.:

09/943769

Inventors:

Sidney L. Andress - Glendale AZ
Wayne R. Buzby - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1100

US Classification:

714 24, 714 15

Abstract:

When a fault-on-fault condition arises in a data processing system which follows a backup fault procedure in the fault handling process, control is passed to dedicated firmware. Fault flags are reset and information vital to maintaining operating system control is sent to a reserved memory (which can be written to in limited circumstances) under firmware control. Control is then transferred to an Intercept process resident in the reserved memory which attempts to build a stable environment for the operating system to dump the system memory. If possible, a dump is taken, and a normal operating system restart is carried out. If not possible, a message with the vital fault information is issued, and a full manual restart must be taken. Even in the latter case, the fault information is available to help in determining the cause of the fault-on-fault.

US Patent:

6868483, Mar 15, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/256289

Inventors:

Wayne R. Buzby - Phoenix AZ, US
Charles P. Ryan - Phoenix AZ, US

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F012/00

US Classification:

711121, 711130, 711135, 711138, 711141, 711142, 711143, 711147, 711118, 711152

Abstract:

In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and second private caches being coupled to the first shared cache and to one another via a first internal bus, and the third and fourth private caches being coupled to the second shared cache and to one another via a second internal bus; method and apparatus for preventing hogging of ownership of a gateword stored in the main memory and which governs access to common code/data shared by processes running in at least three of the processors. Each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use.

US Patent:

6970977, Nov 29, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/403703

Inventors:

Wayne R. Buzby - Phoenix AZ, US
Charles P. Ryan - Phoenix AZ, US
Robert J. Baryla - Phoenix AZ, US
William A. Shelly - Phoenix AZ, US
Lowell D. McCulley - Phoenix AZ, US

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F012/00

US Classification:

711130, 711122, 711135

Abstract:

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.