Wayne S Eng from San Francisco, CA, age 95

Resumes

Property Loss Control Consultant

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Location:

Berkeley, CA

Industry:

Insurance

Work:

Marsh Risk and Insurance
Property Loss Control Consultant

Education:

University of California, Berkeley
Bachelors, Bachelor of Science, Engineering

Skills:

Engineering
Machinery

Fire Protection Specialist, Pe, Arm

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Location:

San Francisco, CA

Industry:

Insurance

Work:

Fire Protection Consulting
Fire Protection Specialist, Pe, Arm
Aig
Regional Account Engineer
Marsh Mar 1997 - Mar 2012
Marsh Risk Consultant
Kemper 1987 - 1997
Lcr

Education:

University of California, Berkeley
Bachelors, Bachelor of Science, Engineering

Skills:

Fire Protection Engineering
Field Work
Risk Assessment
Workers Compensation
Management
Reinsurance
Enterprise Risk Management
Property and Casualty Insurance
General Insurance
Public Speaking
Brokers
Risk Management
Commercial Insurance
Insurance
Underwriting

Global Head Of Market Strategy | Datacom And Telecommunications

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Location:

Sunnyvale, CA

Industry:

Chemicals

Work:

Alpha & Omega Semiconductor Mar 2007 - May 2018
Director, Product Marketing
Henkel Electronic Materials Llc Mar 2007 - May 2018
Global Head of Market Strategy | Datacom and Telecommunications
Leadis Technology Jun 2004 - Jan 2006
Director, Product Marketing
Mysticom Apr 2002 - Jun 2004
Director, Marketing and China Country Manager
Intel Corporation Nov 2000 - Apr 2002
Director, Marketing

Education:

Stony Brook University 1979 - 1983

Skills:

Product Marketing
Semiconductors
Product Management
Ic
Product Development
Analog
Consumer Electronics
Product Launch
Semiconductor Industry
Start Ups
Go To Market Strategy
Cross Functional Team Leadership
Mixed Signal
Integrated Circuits
Power Management
Channel
Program Management
Electronics
Asic
Strategy
Embedded Systems
Sales
Mobile Devices
Integrated Circuit Design
Crm
Strategic Partnerships
Cmos
Eda
Pcb Design
Competitive Analysis
Soc
Processors
Analog Circuit Design
Manufacturing
Product Lifecycle Management
Product Engineering
Technical Marketing
Engineering Management
Circuit Design
Digital Signal Processors
Customer Relationship Management
Hardware Architecture

Wayne Icenhower P Eng

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Product Marketing And Market Development Executive

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Location:

San Francisco Bay Area

Industry:

Semiconductors

Us Patents

Low Capacitance Transient Voltage Suppressor (Tvs) With Reduced Clamping Voltage
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US Patent:

20140363946, Dec 11, 2014
Filed:

Aug 26, 2014
Appl. No.:

14/469103
Inventors:

- Sunnyvale CA, US
Madhur Bobde - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Jun Hu - San Bruno CA, US
Wayne F. Eng - Danville CA, US
International Classification:

H01L 29/66
H01L 27/02
US Classification:

438380
Abstract:

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

Low Capacitance Transient Voltage Suppressor (Tvs) With Reduced Clamping Voltage
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US Patent:

20140134825, May 15, 2014
Filed:

Jan 16, 2014
Appl. No.:

14/157416
Inventors:

- Sunnyvale CA, US
Madhur Bobde - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Jun Hu - San Bruno CA, US
Wayne F. Eng - Danville CA, US
Assignee:

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:

H01L 21/822
H01L 21/265
H01L 21/762
US Classification:

438430, 438435
Abstract:

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.