Wayne F Eng

US Patent:

20130001694, Jan 3, 2013

Filed:

Jun 28, 2011

Appl. No.:

13/170965

Inventors:

Lingpeng Guan - San Jose CA, US
Madhur Bobde - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Jun Hu - San Bruno CA, US
Wayne F. Eng - Danville CA, US

Assignee:

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 23/60
H01L 21/336

US Classification:

257355, 438268, 257E23002, 257E21409

Abstract:

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

US Patent:

20160049876, Feb 18, 2016

Filed:

Aug 12, 2014

Appl. No.:

14/458104

Inventors:

- Sunnyvale CA, US
James Park - Seoul, KR
Xiaotian Zhang - San Jose CA, US
Benjamin Pun - Santa Clara CA, US
Yu Ding - Shanghai, CN
Alex Kim - Seoul, KR
Wayne F. Eng - Danville CA, US
Kuang Ming Chang - Fremont CA, US
Xiaobin Wang - San Jose CA, US

International Classification:

H02M 3/335

Abstract:

A synchronous rectifier comprising a discrete switching device and a controller for controlling the discrete switching device both mounted on a common die pad and packaged in a single package. The packaging of the discrete switching device and the controller together in a single package provides shortest path of connection between the ports of the controller and the switching device, enabling the controller to accurately sense voltage across the switching device thereby avoiding the effect of parasitic inductances and enabling the controller to enable/disable the switching device at the precise time, resulting in improved power consumption and better efficiency.

US Patent:

20140363946, Dec 11, 2014

Filed:

Aug 26, 2014

Appl. No.:

14/469103

Inventors:

- Sunnyvale CA, US
Madhur Bobde - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Jun Hu - San Bruno CA, US
Wayne F. Eng - Danville CA, US

International Classification:

H01L 29/66
H01L 27/02

US Classification:

438380

Abstract:

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

US Patent:

20140134825, May 15, 2014

Filed:

Jan 16, 2014

Appl. No.:

14/157416

Inventors:

- Sunnyvale CA, US
Madhur Bobde - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Jun Hu - San Bruno CA, US
Wayne F. Eng - Danville CA, US

Assignee:

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 21/822
H01L 21/265
H01L 21/762

US Classification:

438430, 438435

Abstract:

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.