Wayne D Kever

US Patent:

6640283, Oct 28, 2003

Filed:

Jan 16, 2002

Appl. No.:

10/050736

Inventors:

Samuel Naffziger - Fort Collins CO
Wayne Kever - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

711118, 711122, 711128, 711133

Abstract:

A compression engine for a cache memory subsystem has a pointer into cache tag memory and cache data memory and an interface coupled to the pointer and capable of being coupled to cache tag memory, and cache data memory. The interface reads tag information and uncompressed data from the cache and writes modified tag information and compressed data to the cache. The compression engine also has compression logic for generating compressed data and generate compression successful information, and tag line update circuitry for generating modified tag information according to the compression successful information and the tag information. Also disclosed is a cache subsystem for a computer system embodying the compression engine, and a method of compressing cache using the compression engine.

US Patent:

6643828, Nov 4, 2003

Filed:

Dec 14, 2001

Appl. No.:

10/016861

Inventors:

Samuel D. Naffziger - Fort Collins CO
Wayne D. Kever - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 2

Abstract:

A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.

US Patent:

6645841, Nov 11, 2003

Filed:

Nov 16, 2001

Appl. No.:

10/016039

Inventors:

Wayne Kever - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 2144

US Classification:

438598, 438599, 438600, 438601, 438 15, 438108

Abstract:

Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

US Patent:

6735673, May 11, 2004

Filed:

Jan 10, 2002

Appl. No.:

10/043789

Inventors:

Wayne Kever - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711118, 709247, 710 68

Abstract:

A method for storing lines of data in a data array of a cache memory mapped to a main memory of a processing system. The data array includes data storage lines having equal lengths. The method includes compressing at least one of the lines of data, fitting the compressed line of data within a subsection of one of the data storage lines, and pointing to the subsection using a tag array. When lines of data are stored in compressed form, more lines can fit into the cache, and a probability of a cache hit is increased.

US Patent:

6895497, May 17, 2005

Filed:

Mar 6, 2002

Appl. No.:

10/092714

Inventors:

Eric S. Fetzer - Longmont CO, US
Wayne Kever - Fort Collins CO, US
Eric DeLano - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F009/38

US Classification:

712215, 712 23

Abstract:

A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

US Patent:

6933611, Aug 23, 2005

Filed:

Jul 29, 2003

Appl. No.:

10/629055

Inventors:

Wayne Kever - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L023/48
H01L023/52
H01L029/40
H01L021/44

US Classification:

257778, 438598, 438599, 438600, 438601

Abstract:

Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

US Patent:

7055114, May 30, 2006

Filed:

Oct 8, 2003

Appl. No.:

10/681815

Inventors:

Wayne Dervon Kever - Fort Collins CO, US
Kenneth Koch, II - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 17/50

US Classification:

716 2, 716 11

Abstract:

Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

US Patent:

20030076729, Apr 24, 2003

Filed:

Oct 24, 2001

Appl. No.:

10/045310

Inventors:

Eric Fetzer - Longmont CO, US
Wayne Kever - Ft Collins CO, US

International Classification:

G11C005/00

US Classification:

365/227000

Abstract:

A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to individual memory sections of a semiconductor memory array. Individual sections of memory are isolated from a fixed power supply by inserting one or more PFETs between a fixed power supply and a positive connection, VDD, of an individual memory section. The voltage applied to each memory section is controlled by applying a separate variable voltage to each gate of all PFETs connected to a particular memory section. If a memory section is not accessed, the voltage to that section can be lowered, saving power. If a memory section is accessed, the voltage to that section may be raised, providing more power and shortening read and write times.