Wei Neng Lee

US Patent:

6351039, Feb 26, 2002

Filed:

May 28, 1998

Appl. No.:

09/087457

Inventors:

Changming Jin - Plano TX
Kelly J. Taylor - Allen TX
Wei William Lee - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257759, 257760, 438623, 438624

Abstract:

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

US Patent:

6383870, May 7, 2002

Filed:

Jun 28, 2001

Appl. No.:

09/895594

Inventors:

Kemal Tamer San - Plano TX
Wei William Lee - Plano TX
Cetin Kaya - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438257, 438595, 438258, 438972

Abstract:

A transistor is formed on an outer surface of a substrate The transistor comprises a floating gate and a control gate An outer encapsulation layer and sidewall bodies and comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies and and the layer can be used as an etch stop during the formation of a drain contact. These layers will also permit the transmission of ultraviolet radiation to the floating gate to enable the erasure of floating gate.

US Patent:

6436746, Aug 20, 2002

Filed:

Jan 5, 1999

Appl. No.:

09/225405

Inventors:

Amitava Chatterjee - Plano TX
Wei William Lee - Plano TX
Greg A. Hames - Dallas TX
Qizhi He - Plano TX
Maureen Hanratty - Dallas TX
Iqbal Ali - San Jose CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21338

US Classification:

438183, 438197, 438299, 438301, 438585

Abstract:

A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer ( ) may be formed adjacent a substrate ( ). A disposable gate ( ) may be formed adjacent the primary insulation layer ( ). An isolation dielectric layer ( ) may be formed adjacent the primary insulation layer ( ). The disposable gate ( ) may be removed to expose a portion of the primary insulation layer ( ). The exposed portion of the primary insulation layer ( ) may be removed to expose a portion of the substrate ( ). The primary insulation layer ( ) may be selectively removable relative to the isolation dielectric layer ( ). A gate insulator ( ) may be formed on the exposed portion of the substrate ( ). A gate ( ) may be formed adjacent the gate insulator ( ).

US Patent:

6559050, May 6, 2003

Filed:

Oct 19, 2000

Appl. No.:

09/691907

Inventors:

William R. McKee - Plano TX
Dirk N. Anderson - Plano TX
Wei Lee - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438656, 438629, 438648, 438666, 438672, 438685

Abstract:

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i. e. , exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via.

US Patent:

6635229, Oct 21, 2003

Filed:

Aug 18, 2000

Appl. No.:

09/642199

Inventors:

Wei W. Lee - Plano TX
Albert H-B Cheng - Richardson TX
Qizhi He - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

C01B 724

US Classification:

423240R

Abstract:

A method of reducing perfluorocarbon emissions wherein a plasma reactor or thermal chamber is provided and a gaseous single halogen-containing perfluorocarbon is entered into the reactor or thermal chamber. The perfluorocarbon is altered in the plasma reactor or thermal chamber to one of a bromine-containing and/or iodine-containing carbon species and expelled from the reactor or thermal chamber. The alteration includes entering into the plasma reactor or thermal chamber a species taken from the class consisting of iodine, bromine, hydrogen iodide, hydrogen bromide, bromocarbon compound and iodocarbon compounds. When the reactor is a thermal chamber, the temperature in the thermal chamber is at least 800Â C. and the single halogen-containing species is located in the chamber for from about 1 minute to about 3 minutes. When the reactor is a plasma reactor, a plasma is provided in the plasma reactor to dissociate all of the halogen-containing species in the reactor with the dissociated species combining to form more energetically favorable species which are more environmentally friendly.

US Patent:

6753559, Jun 22, 2004

Filed:

Jul 6, 2001

Appl. No.:

09/899199

Inventors:

Amitava Chatterjee - Plano TX
Wei William Lee - Plano TX
Greg A. Hames - Dallas TX
Qizhi He - Plano TX
Maureen Hanratty - Dallas TX
Iqbal Ali - San Jose CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2980

US Classification:

257283, 438182, 438183, 257284, 257330

Abstract:

A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

US Patent:

6774489, Aug 10, 2004

Filed:

Aug 23, 2001

Appl. No.:

09/938260

Inventors:

Steven W. Russell - Boise ID
Wei William Lee - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257752, 257758, 438633, 438643, 438653

Abstract:

An integrated circuit structure ( ) includes a plurality of solid state electronic devices and a plurality of conductive elements ( ) that electrically couple the electronic devices. The integrated circuit structure ( ) also includes a dielectric layer ( ) positioned between two or more of the conductive elements ( ). A liner ( ) is positioned between at least a portion of the dielectric layer ( ) and a conductive element ( ). The liner ( ) is formed from a compound that includes silicon and either carbon and nitrogen.

US Patent:

6800928, Oct 5, 2004

Filed:

May 28, 1998

Appl. No.:

09/087234

Inventors:

Wei William Lee - Plano TX
Richard Scott List - Beaverton OR
Changming Jin - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2358

US Classification:

257632, 257638, 257644, 257650

Abstract:

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).