Wei Tang

US Patent:

20130115383, May 9, 2013

Filed:

Nov 6, 2012

Appl. No.:

13/669571

Inventors:

Xinliang Lu - Fremont CA, US
David Thompson - San Jose CA, US
Jeffrey W. Anthis - San Jose CA, US
Mei Chang - Saratoga CA, US
Seshadri Ganguli - Sunnyvale CA, US
Wei Tang - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Atif Noori - Saratoga CA, US

International Classification:

C23C 16/455

US Classification:

427535, 4272481, 427250

Abstract:

Provided are methods of depositing pure metal and aluminum alloy metal films. Certain methods comprises contacting a substrate surface with first and second precursors, the first precursor comprising an aluminum precursor selected from dimethylaluminum hydride, alane coordinated to an amine, and a compound having a structure represented by:wherein R is a C1-C6 alkyl group, and the second precursor comprising a metal halide. Other methods relate to sequentially exposing a substrate to a first and second precursor, the first precursor comprising an aluminum precursor as described above, and the second precursor comprising Ti(NR′)or Ta(NR′), wherein R′ is an alkyl, alkenyl, alkynyl, keto or aldehyde group.

US Patent:

20130221445, Aug 29, 2013

Filed:

Feb 20, 2013

Appl. No.:

13/771236

Inventors:

Yu Lei - Foster City CA, US
Srinivas Gandikota - Santa Clara CA, US
Xinyu Fu - Fremont CA, US
Wei Tang - Santa Clara CA, US
Atif Noori - Saratoga CA, US

International Classification:

H01L 21/28
H01L 29/49

US Classification:

257368, 438592

Abstract:

Provided are devices and methods utilizing TiN and/or TaN films doped with Si, Al, Ga, Ge, In and/or Hf. Such films may be used as a high-k dielectric cap layer, PMOS work function layer, aluminum barrier layer, and/or fluorine barrier. These TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN films can be used where TiN and/or TaN films are traditionally used, or they may be used in conjunction with TiN and/or TaN.

US Patent:

20130295759, Nov 7, 2013

Filed:

Apr 18, 2013

Appl. No.:

13/865285

Inventors:

Xinliang Lu - Fremont CA, US
Seshadri Ganguli - Sunnyvale CA, US
Atif Noori - Saratoga CA, US
Maitreyee Mahajani - Saratoga CA, US
Shih Chung Chen - Cupertino CA, US
Yu Lei - Foster City CA, US
Xinyu Fu - Fremont CA, US
Wei Tang - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US

International Classification:

H01L 29/66

US Classification:

438591

Abstract:

Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.

US Patent:

20230057756, Feb 23, 2023

Filed:

Aug 15, 2022

Appl. No.:

17/888014

Inventors:

- Ann Arbor MI, US
Wei TANG - Fremont CA, US

Assignee:

THE REGENTS OF THE UNIVERSITY OF MICHIGAN - Ann Arbor MI

International Classification:

G11C 11/54
G06N 20/10
G06N 3/063
G11C 13/00
G06F 7/544

Abstract:

A method is presented for mapping weights for kernels of a neural network onto a crossbar array. In one example, the crossbar array is comprised of an array of non-volatile memory cells arranged in columns and rows, such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line; and wherein each memory cell is configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and a weight of the given memory cell onto the corresponding bit line of the given memory cell, where the value of the multiplier is encoded in the input signal and the weight of the given memory cell is stored by the given memory cell.

US Patent:

20230005945, Jan 5, 2023

Filed:

Sep 9, 2022

Appl. No.:

17/941421

Inventors:

- Santa Clara CA, US
Yixiong Yang - Fremont CA, US
Yong Wu - Sunnyvale CA, US
Wei V. Tang - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Yongjing Lin - San Jose CA, US
Karla M Bernal Ramos - San Jose CA, US
Shih Chung Chen - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 27/11556
H01L 21/285
H01L 21/67
H01L 21/28
C23C 16/06
H01L 21/311
C23C 16/50
C23C 16/455
H01L 29/423

Abstract:

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

US Patent:

20200373318, Nov 26, 2020

Filed:

May 18, 2020

Appl. No.:

16/876280

Inventors:

- Santa Clara CA, US
Yixiong Yang - Fremont CA, US
Yong Wu - Sunnyvale CA, US
Wei V. Tang - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Yongjing Lin - San Jose CA, US
Karla M. Barnal Ramos - San Jose CA, US
Shih Chung Chen - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 27/11556
H01L 21/285
H01L 21/67
H01L 21/28
H01L 29/423
H01L 21/311
C23C 16/50
C23C 16/455
C23C 16/06

Abstract:

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

US Patent:

20190341268, Nov 7, 2019

Filed:

May 1, 2019

Appl. No.:

16/400248

Inventors:

- Santa Clara CA, US
Yixiong Yang - Fremont CA, US
Mario D. Sanchez - San Jose CA, US
Guoqiang Jian - San Jose CA, US
Wei Tang - Santa Clara CA, US
Paul F. Ma - Scottsdale AZ, US

International Classification:

H01L 21/3213
H01L 29/49

Abstract:

Processing methods comprising etching a metal nitride layer with an etchant. The etchant can be, for example, WCl, WOClor TaCl. Methods of improving the selectivity of etch processes are also disclosed.

US Patent:

20180308690, Oct 25, 2018

Filed:

Apr 16, 2018

Appl. No.:

15/954521

Inventors:

- Fremont CA, US
Wei Tang - Fremont CA, US

International Classification:

H01L 21/02
H01L 21/768
H01L 21/324
H01L 21/3105
C23C 16/04
C23C 16/56

Abstract:

Methods of densifying films, cross-linking films, and controlling the stress of films are provided herein. Methods include forming a removable film on a substrate comprising a material to be densified, and annealing the substrate to transfer stress from the removable film to the material and thereby densify the material. Some methods involve depositing a tensile capping layer on the material to be densified on a substrate and annealing the substrate at a temperature greater than about 450 C. Some methods include clamping the substrate including the material to be densified to a shaped pedestal using an electrostatic chuck to apply compressive stress to the material to be densified.