Wen Xiu Lin

US Patent:

7524739, Apr 28, 2009

Filed:

Feb 22, 2007

Appl. No.:

11/677871

Inventors:

Wen Lin - Emmaus PA, US

Assignee:

S.O.I.Tec Silicon on Insulator Technologies - Bernin

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438479, 438478, 438481, 438482, 257E21001, 257E21598

Abstract:

The invention relates to a method of improving a surface of a semiconductor substrate which is at least partially made of silicon. Defects present in or on the semiconductor substrate can be really repaired to provide a semiconductor substrate with a high surface quality. This is achieved by a selective epitaxial deposition in the at least one hole in the surface of the semiconductor substrate. Generally, the deposition step is preceded by an etching step which removes the defects and leaves behind at least one hole that can be plugged or filled with the selective epitaxial deposition of silicon to repair the substrate.

US Patent:

7639048, Dec 29, 2009

Filed:

Jul 28, 2005

Appl. No.:

11/815377

Inventors:

Wen T. Lin - Spring House PA, US

Assignee:

Keystone Semiconductor, Inc. - Spring House PA

International Classification:

H03D 13/00

US Classification:

327 3, 327 7

Abstract:

A system and method for detecting a phase and a frequency and an arrival-time difference between two signals ( and ) that minimizes delay and jitter, and has stable operation even when the two signals ( and ) are essentially identical. The system includes two single-ended charge-pump (), phase-frequency detection (PFD) circuits (). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit () ensures that the first activated PFD controls the polarity a single-ended charge pump () for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

US Patent:

7817459, Oct 19, 2010

Filed:

Jan 24, 2008

Appl. No.:

12/019391

Inventors:

Wen T. Lin - Ambler PA, US

Assignee:

Keystone Semiconductor Inc. - Spring House PA

International Classification:

G11C 11/00

US Classification:

365154, 365156

Abstract:

Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

US Patent:

8116120, Feb 14, 2012

Filed:

Sep 29, 2010

Appl. No.:

12/893570

Inventors:

Wen T. Lin - Spring House PA, US

International Classification:

G11C 11/00

US Classification:

365154, 365156

Abstract:

Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

US Patent:

20090041173, Feb 12, 2009

Filed:

Nov 14, 2006

Appl. No.:

12/093662

Inventors:

Wen T. Lin - Ambler PA, US

International Classification:

H04L 7/00

US Classification:

375374

Abstract:

This patent disclosure presents circuits, systems and methods to extract the clock signal from a data stream. This new invention is far better than the current technologies in the range of frequency locking and tracking. Since the new data clock recovery system is built by digital circuits only, it can be implemented inside an IC easily. This invention is especially helpful for high speed data communication products since the clock can be recovered at full data rate.

US Patent:

20090135885, May 28, 2009

Filed:

Nov 7, 2006

Appl. No.:

12/092742

Inventors:

Wen T. Lin - Ambler PA, US

Assignee:

KEYSTONE SEMICONDUCTOR, INC. - Bethlehem PA

International Classification:

H04B 1/69

US Classification:

375130, 375E01001

Abstract:

This patent disclosure presents circuits, systems and methods to spread a clock signal to produce a random spreading for the clock signal that offers the maximum possible power density reduction for the spurious radiations generated from the clock signal and its harmonics. These new inventions utilize a non-linear feedback control loop to assist in generation of the spread spectrum clock and result in electronic products that can pass the FCC requirements for spurious radiations generated by the clock signal and its harmonics without utilizing expensive shielding and other EMI suppression methods.

US Patent:

20090267837, Oct 29, 2009

Filed:

May 4, 2006

Appl. No.:

11/913731

Inventors:

Wen T. Lin - Ambler PA, US

International Classification:

G01S 1/24

US Classification:

342387

Abstract:

This patent disclosure presents circuits, systems and methods to produce a stable signal from a reference signal source. These new inventions are far better than the current technologies to provide a stable signal with less phase noises. This new invention also provides a new approach to analyze the feedback control loop without using the traditional feedback control theory.

US Patent:

20100176852, Jul 15, 2010

Filed:

Sep 28, 2007

Appl. No.:

12/443553

Inventors:

Wen T. Lin - Ambler PA, US

International Classification:

H03L 7/06

US Classification:

327155

Abstract:

A new technique using arrival locked loop technology to produce a spread spectrum clock signal with random frequency modulation and with precise variable frequency spread is presented. The arrival locked loop includes three modules, the arrival comparator with a precise spread control, the loop filter and the VCO. An arrival locked loop is made unstable and oscillates at a certain frequency to produce a low frequency modulation signal on the final error correction output to spread the high frequency output signal from VCO in frequency. The period of frequency spread in each cycle of the low frequency modulation signal also increases by a small random amount of time cycle after cycle until the period of frequency spread becomes so long that cycle-slip is produced to the punctual signal at the input of arrival comparator to reset the period of frequency spread to a small amount.