Wesley C Natzle

US Patent:

6335261, Jan 1, 2002

Filed:

May 31, 2000

Appl. No.:

09/584355

Inventors:

Wesley Natzle - New Paltz NY
Richard A. Conti - Mount Kisco NY
Laertis Economikos - Wappingers Falls NY
Thomas Ivers - Hopewell Jct. NY
George D. Papasouliotis - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438435, 438221, 438424, 438685, 438694, 438696, 438758, 438762, 438765, 438775, 438788

Abstract:

A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.

US Patent:

6353249, Mar 5, 2002

Filed:

May 25, 2001

Appl. No.:

09/866239

Inventors:

Diane Catherine Boyd - Lagrangeville NY
Hussein Ibrahim Hanafi - Basking Ridge NJ
Meikei Ieong - Wappingers Falls NY
Wesley Charles Natzle - New Paltz NY

Assignee:

International Businsess Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

257369, 257368, 257327

Abstract:

Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0. 35 fF/m or below) and a channel length (sub-lithographic, e. g. , 0. 1 m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

US Patent:

6635923, Oct 21, 2003

Filed:

May 24, 2001

Appl. No.:

09/866023

Inventors:

Hussein I. Hanafi - Basking Ridge NJ
Jeffrey J. Brown - Fishkill NY
Wesley C. Natzle - New Paltz NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257327, 257329, 257347, 257350, 257351, 257401

Abstract:

A technique for forming a sub-0. 05 m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

US Patent:

6656824, Dec 2, 2003

Filed:

Nov 8, 2002

Appl. No.:

10/291353

Inventors:

Hussein I. Hanafi - Basking Ridge NJ
Wesley Natzle - New Paltz NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 213205

US Classification:

438585, 438592, 438595

Abstract:

The present invention provides a method for fabricating low-resistance, sub-0. 1 m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH or a plasma containing HF and NH.

US Patent:

6660598, Dec 9, 2003

Filed:

Feb 26, 2002

Appl. No.:

10/084550

Inventors:

Hussein I. Hanafi - Basking Ridge NJ
Diane C. Boyd - LaGrangeville NY
Kevin K. Chan - Staten Island NY
Wesley Natzle - New Paltz NY
Leathen Shi - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438291, 438289, 438301

Abstract:

A sub-0. 05 m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

US Patent:

6774000, Aug 10, 2004

Filed:

Nov 20, 2002

Appl. No.:

10/300239

Inventors:

Wesley C. Natzle - New Paltz NY
Marc W. Cantell - Sheldon VT
Louis D. Lanzerotti - Charlotte VT
Effendi Leobandung - Wappingers Falls NY
Brian L. Tessier - Poughkeepsie NY
Ryan W. Wuthrich - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438300

Abstract:

A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

US Patent:

6790733, Sep 14, 2004

Filed:

Mar 28, 2003

Appl. No.:

10/249296

Inventors:

Wesley C. Natzle - New Paltz NY
Bruce B. Doris - Brewster NY
Sadanand V. Deshpande - Fishkill NY
Renee T. Mo - White Plains NY
Patricia A. ONeil - Newburgh NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438300, 438303, 438595, 438976

Abstract:

The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

US Patent:

6835614, Dec 28, 2004

Filed:

Jun 30, 2003

Appl. No.:

10/609815

Inventors:

Hussein I. Hanafi - Basking Ridge NJ
Jeffrey J. Brown - Fishkill NY
Wesley C. Natzle - New Paltz NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218238

US Classification:

438212, 438149, 438479

Abstract:

A technique for forming a sub-0. 05 m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.