William Franklin Apple

US Patent:

49759299, Dec 4, 1990

Filed:

Sep 11, 1989

Appl. No.:

7/405799

Inventors:

William R. Apple - San Jose CA
William R. Freeman - Richmond CA
Paulmer M. Soderberg - Menlo Park CA

Assignee:

Raynet Corp. - Menlo Park CA

International Classification:

H03D 324

US Classification:

375119

Abstract:

A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

US Patent:

49598465, Sep 25, 1990

Filed:

Sep 11, 1989

Appl. No.:

7/405806

Inventors:

William R. Apple - San Jose CA
William R. Freeman - Richmond CA
Paulmer M. Soderberg - Menlo Park CA
Lyle Thompson - Hayward CA
Mark S. Thomas - Sunnyvale CA

Assignee:

Raynet Corporation - Menlo Park CA

International Classification:

H04L 700

US Classification:

375118

Abstract:

A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.