William T Armstrong

US Patent:

6467007, Oct 15, 2002

Filed:

May 19, 1999

Appl. No.:

09/314769

Inventors:

Troy David Armstrong - Rochester MN
William Joseph Armstrong - Kasson MN
Naresh Nayar - Rochester MN
Kenneth Charles Vossen - Kasson MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1324

US Classification:

710260, 710266, 711166, 713 1, 714 23, 714763

Abstract:

An apparatus, program product, and method utilize a memory access interrupt to effect a reset of a processor in a multi-processor environment. Specifically, a source processor is permitted to initiate a reset of a target processor simply by generating both a reset request and a memory access interrupt for the target processor. The target processor is then specifically configured to detect the presence of a pending reset request during handing of the memory access interrupt, such that the target processor will perform a reset operation responsive to detection of such a request.

US Patent:

6681240, Jan 20, 2004

Filed:

May 19, 1999

Appl. No.:

09/314541

Inventors:

William Joseph Armstrong - Kasson MN
Lynn Allen McMahon - Rochester MN
Jeffrey Jay Scheel - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

709104, 709226, 712 13

Abstract:

A partitioner for creating logical partitions allows a user to specify maximum interactive performance in one partition independently of maximum interactive performance of other partitions to arrive at logical partitions that may be much different than the maximum overall interactive performance percentage of the computer system itself. First, the maximum interactive performance for a computer system is specified, and resources are allocated accordingly. Next, logical partitions may be created, which initially reflect the maximum interactive performance for the computer system as a whole. Finally, the maximum interactive performance can be specified for a partition independently of the interactive performance in other partitions. In this manner a computer system that is configured as a server system with low interactive and high batch performance can have two different partitions, one that has very low interactive performance and the other that balances interactive and batch processing. In this manner two partitions that have greatly different performance attributes can be defined within the limitations of the specified interactive and batch performance for the computer system as a whole.

US Patent:

6691146, Feb 10, 2004

Filed:

May 19, 1999

Appl. No.:

09/314214

Inventors:

Troy David Armstrong - Rochester MN
William Joseph Armstrong - Kasson MN
Michael Joseph Corrigan - Rochester MN
Naresh Nayar - Rochester MN
Thomas Rembert Sand - Rochester MN
Jeffrey Jay Scheel - Rochester MN
Erik Tkal - Rochester MN
Kenneth Charles Vossen - Kasson MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

709100, 709329, 709224

Abstract:

A partition manager for managing logical partitions in a computer system includes hooks to low-level operating system code in one of the logical partitions. By using the operating system code to manage the resources of a computer system, any changes that are made to the operating system are automatically reflected in the function of the partition manager. In addition, low-level functions of operating systems, which are often well-debugged and tested, can be used when generating a new partition manager, greatly simplifying the time and reducing the cost of producing a partition manager.

US Patent:

6711700, Mar 23, 2004

Filed:

Apr 23, 2001

Appl. No.:

09/840345

Inventors:

Troy David Armstrong - Rochester MN
William Joseph Armstrong - Mantorville MN
Stephanie Maria Forsman - Rochester MN
Naresh Nayar - Rochester MN
Jeffrey Jay Scheel - Rochester MN
Andy Wottreng - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 23, 714 10, 714 55, 712 13

Abstract:

An apparatus and method for monitoring the state of a computer system running multiple operating systems shared by a partition manager is provided. A dedicated service processor monitors the individual run state condition of a plurality of processors running a plurality of operating systems. The service processor executes a routine to poll a memory location in each processor in the system to determine if the processor has entered an error loop with interrupts disabled. If any one of the plurality of processors are in an error loop, the service processor executes a routine to send a non-maskable interrupt to the looped processor so that the partition manager may regain control of the processor.

US Patent:

6785887, Aug 31, 2004

Filed:

Dec 27, 2000

Appl. No.:

09/749107

Inventors:

William Joseph Armstrong - Mantorville MN
Naresh Nayar - Rochester MN
Kenneth Charles Vossen - Mantorville MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 946

US Classification:

718100, 718107, 718108

Abstract:

A method of handling conflicts between threads, including an initiating thread and at least one other thread, for at least one shared resource in a multi-threaded processing system having a processor and memory includes setting a location in memory for each other thread on the processor with the initiating thread. The initiating thread signals an inter-processor interrupt (IPI) to all other threads on the processor. For each other thread, an interrupt handler is initiated where each other thread: acknowledges receipt of the interrupt, and proceeds to spin on the respective location in memory that was set, thereby guaranteeing that the respective other thread will not be using any shared resource of the processor. The initiating thread waits for other threads on processor to acknowledge the inter-processor interrupt (IPI), and when all the other threads have acknowledged the inter-processor interrupt (IPI), the initiating thread proceeds to save the state of the shared resource in memory, sets the shared resource to the state wanted, uses the shared resource, and restores the original state of the resource. The initiating thread then releases the other threads from their spin by resetting the location in memory that was set above.

US Patent:

6957435, Oct 18, 2005

Filed:

Apr 19, 2001

Appl. No.:

09/838057

Inventors:

William Joseph Armstrong - Mantorville MN, US
Mark Gregory Manges - Rochester MN, US
Naresh Nayar - Rochester MN, US
Jeffrey Jay Scheel - Rochester MN, US
Craig Alden Wilcox - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/46

US Classification:

718104, 712 13, 711173

Abstract:

A processor allocation mechanism for a logically partitionable computer system allows an administrator to specify processing capability allocable to each partition as an equivalent number of processors, where the processing capability may be specified as a non-integer value. This processing capability value is unaffected by changes to the processing capability values of other partitions. The administrator may designate multiple sets of processors, assigning each physical processor of the system to a respective processor set. Each logical partition is constrained to execute in an assigned processor set, which may be shared by more than one partition. Preferably, the administrator may designate a logical partition as either capped, meaning that a partition can not use excess idle capacity of the processors, or uncapped, meaning that it can.

US Patent:

6959291, Oct 25, 2005

Filed:

May 19, 1999

Appl. No.:

09/314324

Inventors:

William Joseph Armstrong - Kasson MN, US
Naresh Nayar - Rochester MN, US
Kevin Patrick Stamschror - Wabasha MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/00

US Classification:

705 59, 718100

Abstract:

An apparatus, program product and method track concurrent uses of a computer program across a plurality of logical partitions in a logically partitioned computer, such that a decision as to whether to grant or deny a request to use the computer program in a particular logical partition may be made based upon whether the requested use, coupled with other uses in other logical partitions in the computer, would violate a concurrent use software license associated with the computer program. As such, the license restrictions of a concurrent use software license can be enforced on a logically partitioned computer regardless of the particular logical partitions within which a computer program executes.

US Patent:

6990560, Jan 24, 2006

Filed:

Jan 16, 2003

Appl. No.:

10/346010

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael Joseph Corrigan - Rochester MN, US
Gary Ross Ricard - Chatfield MN, US
Timothy Joseph Torzewski - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711152

Abstract:

A task synchronization mechanism operates on a global lock that is shared between processors an on local locks that are not shared between processors. The local locks are processor-specific locks. Each processor-specific lock is dedicated to a particular processor in the system. When shared access to a resource is required, a processor updates its processor-specific lock to indicate the processor is sharing the resource. Because each processor-specific lock is dedicated to a particular processor, this eliminates a significant portion of the memory bus traffic associated with all processors reading and updating the same lock. When exclusive access to a resource is required, the requesting processor waits until the count of all processor-specific locks indicate that none of these processors have a lock on the resource. Once no processor has a lock on the resource, exclusive access to the resource may be granted.