William G Baldwin

US Patent:

6528974, Mar 4, 2003

Filed:

Sep 26, 2000

Appl. No.:

09/669357

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mtn View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G05F 1577

US Classification:

323267, 327115

Abstract:

A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

US Patent:

6608476, Aug 19, 2003

Filed:

Sep 26, 2000

Appl. No.:

09/670143

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mtn View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 1132

US Classification:

324103R, 324142, 713501, 713300, 713322

Abstract:

A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.

US Patent:

6691215, Feb 10, 2004

Filed:

Sep 26, 2000

Appl. No.:

09/670418

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mountain View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711167, 713400, 713600, 327147

Abstract:

A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

US Patent:

6700421, Mar 2, 2004

Filed:

Sep 26, 2000

Appl. No.:

09/669825

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mountain View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03L 706

US Classification:

327159, 327156

Abstract:

A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal.

US Patent:

6718473, Apr 6, 2004

Filed:

Sep 26, 2000

Appl. No.:

09/670420

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mountain View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06R 132

US Classification:

713320, 375327, 375376

Abstract:

In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.

US Patent:

6728890, Apr 27, 2004

Filed:

Sep 26, 2000

Appl. No.:

09/670417

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mountain View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06R 126

US Classification:

713300, 710107, 710240

Abstract:

A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

US Patent:

6738915, May 18, 2004

Filed:

May 12, 2000

Appl. No.:

09/569535

Inventors:

James A. Mott - Oakland CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 126

US Classification:

713330

Abstract:

An apparatus and method for enabling hot swapped circuit boards to receive multiple power voltages from a backplane and supply the multiple power voltages to devices on the circuit board in a predictable sequence. An apparatus according to the invention would include a circuit board having an electrical connector, a sequencing circuit, and an element. The electrical connector of the circuit board receives the multiple power voltages from another circuit board, such as a backplane or motherboard. The sequencing circuit receives the multiple power voltages from the electrical connector. When a part of the sequencing circuit receives a signal indicating that the sequencing circuit has received a first power voltage, the sequencing circuit provides a second power voltage to the element electrically coupled to the sequencing circuit.

US Patent:

6748546, Jun 8, 2004

Filed:

Sep 26, 2000

Appl. No.:

09/670041

Inventors:

Russell N. Mirov - Los Altos CA
Michel Cekleov - Mountain View CA
Mark Young - Mountain View CA
William M. Baldwin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 126

US Classification:

713320, 713300, 713323

Abstract:

A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.