William Thomas Boles

US Patent:

20120098690, Apr 26, 2012

Filed:

Oct 22, 2010

Appl. No.:

12/910662

Inventors:

Huseyin DINC - Greensboro NC, US
Michael ELLIOT - Summerfield NC, US
William Thomas BOLES - Greensboro NC, US

Assignee:

ANALOG DEVICES, INC. - Norwood MA

International Classification:

H03M 1/12
H03K 3/037

US Classification:

341155, 327225

Abstract:

A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.