William J Donoghue

US Patent:

7002387, Feb 21, 2006

Filed:

Apr 16, 2004

Appl. No.:

10/825720

Inventors:

William J. Donoghue - Round Rock TX, US
Chadwick N. Marak - Austin TX, US

Assignee:

California Micro Devices - Milpitas CA

International Classification:

H03K 3/12

US Classification:

327199, 327540

Abstract:

A regulator circuit for use with integrated circuits protects downstream devices from the application of unregulated voltages during start-up or other initialization. The circuit includes an op amp which controls a regulator during steady state operation, and also includes a switching portion which responds to a reset signal and disconnects the op amp from the voltage regulator to prevent unregulated voltages from reaching the output node during start-up. During start-up, a current mirror is used to supply an initial voltage reference to the op amp, and upon establishment of steady state operation, the regulator turns off the current mirror and reconnects the op amp to the voltage regulator to allow the op amp and voltage regulator to control the output node.

US Patent:

45946892, Jun 10, 1986

Filed:

Sep 4, 1984

Appl. No.:

6/646718

Inventors:

William J. Donoghue - Round Rock TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1140

US Classification:

365182

Abstract:

A non-volatile memory has a plurality of coupling transistors for coupling bit lines to an equalization line in response to an equalization pulse. The equalization line has capacitance as do the bit lines. Prior to the occurrence of the equalization pulse, the unselected bit lines are charged to a first predetermined voltage, and the equalization line is charged to a second predetermined voltage by a high impedance reference voltage generator. A pulse generator provides the equalization pulse in response to an address transition.

US Patent:

45637539, Jan 7, 1986

Filed:

Sep 4, 1984

Appl. No.:

6/646725

Inventors:

William J. Donoghue - Round Rock TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1140

US Classification:

365104

Abstract:

A virtual ground memory which has four state cells coupled to bit lines has a load directly connected to each bit line to reduce the degradation of the output of a selected memory cell due to voltage drop caused by current flow between load and selected memory cell. Additionally, loads which are coupled to the bit lines are also coupled to an adjacent virtual ground line to avoid providing a separate power supply line for the loads.

US Patent:

62048341, Mar 20, 2001

Filed:

Aug 17, 1994

Appl. No.:

8/292135

Inventors:

Robert C. Baker - Austin TX
William J. Donoghue - Round Rock TX
Stephen H. Kelley - Austin TX
Claude Hilbert - Austin TX

Assignee:

SI Diamond Technology, Inc. - Austin TX

International Classification:

G09G 332

US Classification:

345 74

Abstract:

A system and method for producing uniform energy dissipation in display pixels with widely varying electrical characteristics in order to equalize light output and improve yield within a matrix addressable display panel. The present invention is implemented within a driver circuit utilizing the concept of current integration. A reference voltage, which is proportional to the most efficient pixel within the display is compared to the energy dissipated within a particular pixel during illumination of that pixel. A current mirror circuit supplies a current equivalent to the current provided to the object pixel to an integrator circuit resulting in a rising voltage within the integrator circuit. The rising voltage is proportional to the energy being dissipated within the current pixel. Once the rising voltage is equal to or greater than the reference voltage, current is removed from the object pixel.

US Patent:

46706755, Jun 2, 1987

Filed:

Feb 7, 1986

Appl. No.:

6/827836

Inventors:

William J. Donoghue - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 524
G11C 706

US Classification:

307530

Abstract:

A sense amplifier detecting a small current differential between a selected memory cell and a reference cell in a memory array includes a first pass transistor, a second pass transistor, a cross-coupled transistor arrangement and a differential amplifier. The cross-coupled transistor arrangement detect a small current differential between a bit sense current line and a bit sense reference current line. The difference current is amplified by the differential amplifier to produce an output data voltage indicative of the binary state of the selected memory cell.

US Patent:

45635994, Jan 7, 1986

Filed:

Mar 28, 1983

Appl. No.:

6/479788

Inventors:

William J. Donoghue - Round Rock TX
Glenn E. Noufer - Colorado Springs CO

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1922
H03K 1908

US Classification:

307448

Abstract:

A circuit uses a pair of transistors in series to provide an output pulse which indicates an address transition has occurred. A duration of joint conductivity of the pair of transistors determines the duration of the output pulse. For an address transition, one of the transistors is rapidly turned on while the other is slowly turned off with a slow fall time. The fall time is adjustable to achieve an adjustable duration of joint conductivity, and thereby an adjustable output pulse width.

US Patent:

44519079, May 29, 1984

Filed:

Oct 26, 1981

Appl. No.:

6/314816

Inventors:

William J. Donoghue - Round Rock TX
Rodney C. Tesch - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700

US Classification:

365203

Abstract:

A pull-up circuit for a memory provides an additional natural transistor between a power supply and diode-connected transistors which reduces the voltage on bit sense lines sufficiently to allow selected column select transistors to turn on prior to a memory cell being enabled. Additional control circuitry further reduces the voltage to the diode-connected transistors when no memory cells have been selected to be enabled to compensate for the reduction in voltage drop across the natural transistor when no current is flowing through it.

US Patent:

43120474, Jan 19, 1982

Filed:

May 29, 1980

Appl. No.:

6/154353

Inventors:

William J. Donoghue - Round Rock TX

Assignee:

Motorola, Inc. - Schaumberg IL

International Classification:

G11C 702

US Classification:

365189

Abstract:

A memory array having improved isolation between the bit sense common lines is provided by using diode connected transistors. The diode connected transistors substantially eliminate any current flow between bit sense common lines when a certain portion of the column select circuitry has not been selected. Since the blocking transistors prevent current flow there is no noise generated to be coupled to one of the control lines. This results in a memory array which can operate at higher speeds since better differential signals are established to be sensed by the sense amplifier.