William H Dufresne

US Patent:

20090249267, Oct 1, 2009

Filed:

Mar 31, 2008

Appl. No.:

12/059096

Inventors:

Eduard Cerny - Worcester MA, US
Surrendra A. Dudani - Newton MA, US
William R. Dufresne - North Attleboro MA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 5

Abstract:

One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to the circuit design. The system performs the simulation by using a finite state automaton (FSA) instance for a temporal coverage property to observe inputs and outputs of the circuit, and by using soft constraints associated with the FSA instance to bias the input stimuli for the circuit design so that the simulation is likely to progress through a sequence of states which satisfy the temporal coverage property.