William George En

age ~54

from Fremont, CA

Also known as:
  • William Ge En
  • William G En
  • William G Nen
  • Bill G En
  • William G Pineda
  • William G George
  • William Gen
  • William Emuakpeje
  • William Geen
  • En William
Phone and address:
40315 Linaria Cir, Fremont, CA 94538

William En Phones & Addresses

  • 40315 Linaria Cir, Fremont, CA 94538
  • Berkeley, CA
  • 495 Alexander Way, Milpitas, CA 95035 • 4089420373
  • 1063 Morse Ave, Sunnyvale, CA 94089
  • Northridge, CA
  • Alameda, CA
  • Santa Clara, CA

Interests

job inquiries

Industries

Semiconductors

Resumes

William En Photo 1

Director At Amd

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Location:
San Francisco Bay Area
Industry:
Semiconductors
Experience:
AMD (Public Company; 10,001+ employees; AMD; Semiconductors industry): Director,  (-) 

Us Patents

  • Methods And Arrangements For Determining An Endpoint For An In-Situ Local Interconnect Etching Process

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  • US Patent:
    6358362, Mar 19, 2002
  • Filed:
    Feb 29, 2000
  • Appl. No.:
    09/515321
  • Inventors:
    William G. En - Sunnyvale CA
    Allison Holbrook - San Jose CA
    Fei Wang - San Jose CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G01I 346
  • US Classification:
    156345, 20419233, 356425
  • Abstract:
    An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.
  • Semiconductor Device Having Uniform Spacers

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  • US Patent:
    6380588, Apr 30, 2002
  • Filed:
    May 9, 2000
  • Appl. No.:
    09/567013
  • Inventors:
    William G. En - Milpitas CA
    Minh Van Ngo - Union City CA
    David K. Foote - San Jose CA
    Scott A. Bell - San Jose CA
    Olov B. Karlsson - San Jose CA
    Christopher F. Lyons - Fremont CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 2100
  • US Classification:
    257345, 257327, 438595
  • Abstract:
    A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
  • Methods And Arrangements For Insulating Local Interconnects For Improved Alignment Tolerance And Size Reduction

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  • US Patent:
    6399480, Jun 4, 2002
  • Filed:
    Feb 29, 2000
  • Appl. No.:
    09/515319
  • Inventors:
    William G. En - Sunnyvale CA
    Darin A. Chan - Campbell CA
    David K. Foote - San Jose CA
    Fei Wang - San Jose CA
    Minh Van Ngo - Union City CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 714263
  • US Classification:
    438630, 438568, 438637, 438639, 438747
  • Abstract:
    At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
  • Method Of Fabrication Of Semiconductor-On-Insulator (Soi) Wafer Having A Si/Sige/Si Active Layer

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  • US Patent:
    6410371, Jun 25, 2002
  • Filed:
    Feb 26, 2001
  • Appl. No.:
    09/794884
  • Inventors:
    Bin Yu - Cupertino CA
    William G. En - Milpitas CA
    Judy Xilin An - San Jose CA
    Concetta E. Riccobene - Mountain View CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 2184
  • US Classification:
    438151, 438311, 438455, 438459, 438977
  • Abstract:
    A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.
  • Silicon-On-Insulator (Soi) Chip Having An Active Layer Of Non-Uniform Thickness

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  • US Patent:
    6414355, Jul 2, 2002
  • Filed:
    Jan 26, 2001
  • Appl. No.:
    09/770708
  • Inventors:
    Judy Xilin An - San Jose CA
    Bin Yu - Cupertino CA
    William G. En - Milpitas CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 2701
  • US Classification:
    257347, 257324
  • Abstract:
    A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.
  • Bonded Soi For Floating Body And Metal Gettering Control

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  • US Patent:
    6433391, Aug 13, 2002
  • Filed:
    Jun 8, 2001
  • Appl. No.:
    09/877631
  • Inventors:
    William George En - Milpitas CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 2900
  • US Classification:
    257347, 257349
  • Abstract:
    A device and method for making a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. An interface between the insulator layer and the semiconductor layer bleeds off extra carriers. Active regions are defined in the semiconductor layer by isolation trenches and the insulator layer.
  • Method Of Making A Multi-Thickness Silicide Soi Device

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  • US Patent:
    6441433, Aug 27, 2002
  • Filed:
    Apr 2, 2001
  • Appl. No.:
    09/824412
  • Inventors:
    William G. En - Milpitas CA
    Srinath Krishnan - Campbell CA
    Bin Yu - Cupertino CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 3113
  • US Classification:
    257344, 257384, 257755, 438299, 438305, 438586, 438630, 438683
  • Abstract:
    A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.
  • Method Of Fabricating A Silicon-On-Insulator (Soi) Chip Having An Active Layer Of Non-Uniform Thickness

    view source
  • US Patent:
    6448114, Sep 10, 2002
  • Filed:
    Apr 23, 2002
  • Appl. No.:
    10/128831
  • Inventors:
    Judy Xilin An - San Jose CA
    Bin Yu - Cupertino CA
    William G. En - Milpitas CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 218234
  • US Classification:
    438142, 438404, 438480, 438164
  • Abstract:
    A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.

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