Bill R Foland

US Patent:

7379452, May 27, 2008

Filed:

Dec 21, 2001

Appl. No.:

10/028871

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7885255, Feb 8, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7957370, Jun 7, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

60210117, Feb 1, 2000

Filed:

Mar 19, 1997

Appl. No.:

8/822603

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan J. Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill R. Foland - Littleton CO
Neal Glover - Broomfield CO
Larry D. King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 51

Abstract:

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

US Patent:

54248817, Jun 13, 1995

Filed:

Feb 1, 1993

Appl. No.:

8/012266

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill Foland - Littleton CO
Neal Glover - Broomfield CO
Larry King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509
G11B 2014
G11B 2016
G06F 1110

US Classification:

360 40

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

58123342, Sep 22, 1998

Filed:

Mar 16, 1994

Appl. No.:

8/210302

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill Foland - Littleton CO
Neal Glover - Broomfield CO
Larry King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 40

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

58447385, Dec 1, 1998

Filed:

Mar 19, 1997

Appl. No.:

8/821175

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan J. Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill R. Foland - Littleton CO
Neal Glover - Broomfield CO
Larry D. King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 44

Abstract:

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.

US Patent:

59781629, Nov 2, 1999

Filed:

Mar 19, 1997

Appl. No.:

8/821174

Inventors:

Richard T. Behrens - Louisville CO
Kent D. Anderson - Westminster CO
Alan J. Armstrong - Longmont CO
Trent Dudley - Littleton CO
Bill R. Foland - Littleton CO
Neal Glover - Broomfield CO
Larry D. King - Boulder CO

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 509

US Classification:

360 53

Abstract:

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc. , for use in calibrating the read channel components and estimating the bit error rate.