William E Grose

US Patent:

6384643, May 7, 2002

Filed:

Nov 22, 2000

Appl. No.:

09/721393

Inventors:

William E. Grose - Plano TX
Eugene G. Dierschke - Dallas TX
Jingwei Xu - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1714

US Classification:

327112, 327333, 327362, 327378, 327513

Abstract:

Driver circuitry ( ) is disclosed, incorporating feedback circuitry ( ) inter-coupled with reference circuitry ( ) to equalize the voltage level of an output ( ) with a reference voltage source ( ) in the reference circuitry; where the driver circuitry comprises a first transistor ( ) having a first terminal coupled to a voltage source ( ), a second terminal coupled to an input ( ), and a third terminal coupled to a resistor ( ), a second transistor ( ) having a first terminal coupled to ground ( ), a second terminal coupled to an input ( ), and a third terminal coupled to a resistor ( ), a third transistor ( ) having a first terminal coupled to the output, a second terminal ( ) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor ( ) coupling the output to a voltage source ( ).

US Patent:

6815757, Nov 9, 2004

Filed:

Jan 22, 2003

Appl. No.:

10/349066

Inventors:

Reed W. Adams - Plano TX
William E. Grose - Plano TX
Sameer Pendharkar - Richardson TX
Roland Bucksch - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29788

US Classification:

257315, 257321, 257322, 257401, 438176, 438197, 438594

Abstract:

Disclosed are devices and associated methods for manufacturing an EEPROM memory cell ( ) for use on a negatively biased substrate ( ). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell ( ) including a DNwell ( ) formed on a P-type substrate ( ) for isolating the EEPROM cell ( ) from the underlying P-type substrate ( ).

US Patent:

6952120, Oct 4, 2005

Filed:

Feb 12, 2004

Appl. No.:

10/777991

Inventors:

MD Abidur Rahman - Allen TX, US
William E. Grose - Plano TX, US
Brett E. Smith - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03B001/00

US Classification:

327108, 327103, 327427

Abstract:

The present invention provides a system () for controlling drive signal timing parameters of an output driver circuit (). The present invention defines a driver circuit having an output interface (), and a first transistor () coupled to a first voltage supply (), a first control signal (), and a first node (). The circuit also has a first resistive element, coupled between the first node and a second node (). A second resistive element () is coupled to ground. A second transistor () is coupled to the second node, to a second control signal (), and the second resistive element. The circuit has a third transistor (), coupled to the first and second nodes, and to a third node (). A third resistive element () is coupled between the third node and the output interface. A fourth transistor () is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (), coupled to a second voltage supply (), to the first node, and to the output interface.

US Patent:

7013725, Mar 21, 2006

Filed:

Mar 14, 2005

Appl. No.:

11/079675

Inventors:

Tobin D. Hagan - Dallas TX, US
David J. Baldwin - Allen TX, US
William E. Grose - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01F 1/68

US Classification:

7320415

Abstract:

In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided. In a particular embodiment, the hot-wire anemometer includes a bridge circuit including a hot-wire resistor, first and second input terminals, and first and second output terminals, the hot-wire resistor having a resistance dependent at least in part on an airflow past the hot-wire resistor. The hot-wire anemometer further includes a first operational amplifier coupled to the output terminals of the bridge circuit, the first operational amplifier operable to generate an output signal in response to a voltage differential across the first and second output terminals of the bridge circuit, and a second operational amplifier operable to generate an output signal in response to the output signal of the first operational amplifier and to a discontinuous time control signal. A switching mechanism cycles a supply voltage to the input terminals of the bridge circuit in response to output signal of the second operational amplifier such that the supply voltage is intermittently connected to the input terminals the bridge circuit, and an inductor coupling the switching mechanism to the first input terminal of the bridge circuit operable to low-pass filter an output voltage of the bridge circuit.

US Patent:

7034512, Apr 25, 2006

Filed:

Oct 8, 2003

Appl. No.:

10/680999

Inventors:

Jingwei Xu - Plano TX, US
Zbigniew J. Lata - Plano TX, US
William E. Grose - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/40

US Classification:

323283, 323351

Abstract:

System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB ), a comparator (such as the comparator ), and a fixed off time logic (FOTL) (such as the FOTL ). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.

US Patent:

7072776, Jul 4, 2006

Filed:

Nov 9, 2004

Appl. No.:

10/985388

Inventors:

Tobin D. Hagan - Dallas TX, US
David J. Baldwin - Allen TX, US
William E. Grose - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/00
G01F 1/68

US Classification:

702 47, 702 50, 7320415, 7320414

Abstract:

A system and method are provided to regulate resistance in a discontinuous time hot-wire anemometer. The solution removes supply voltage dependency on the mass airflow output signal. Operating the hot-wire anemometer using discontinuous time regulation offers lower system power, but introduces an inverse supply dependent term in the associated transfer function. This effect is removed by multiplying the output signal via a supply dependent signal.

US Patent:

7283343, Oct 16, 2007

Filed:

Dec 15, 2004

Appl. No.:

11/015315

Inventors:

William E. Grose - Plano TX, US
Timothy J. Legat - McKinney TX, US
Sanmukh M. Patel - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 3/18

US Classification:

361 84

Abstract:

A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode. A resistor connects between a first output node of the reverse battery protection circuit to provide a voltage drop between the drain terminal and the gate of the p-channel device.

US Patent:

7315971, Jan 1, 2008

Filed:

Oct 4, 2005

Appl. No.:

11/243898

Inventors:

William E. Grose - Plano TX, US
Lonnie L. Lambert - Plano TX, US
Jeanne Krayer Pitz - Richardson TX, US
Toru Tanaka - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00

US Classification:

714718

Abstract:

A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.