William D Guthrie

US Patent:

6492247, Dec 10, 2002

Filed:

Nov 21, 2000

Appl. No.:

09/717970

Inventors:

William H. Guthrie - Essex Junction VT
Andreas Kluwe - Essex Junction VT
Michael Ruprecht - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2146

US Classification:

438460, 438658, 438719, 438680, 501 87, 257639

Abstract:

A method for manufacturing integrated circuits (âICâ) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.

US Patent:

7872897, Jan 18, 2011

Filed:

Apr 30, 2003

Appl. No.:

10/552971

Inventors:

William R. Tonti - Essex Junction VT, US
Wayne S. Berry - Essex Junction VT, US
John A. Fifield - Underhill VT, US
William H. Guthrie - Essex Junction VT, US
Richard S. Kontra - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 17/00

US Classification:

365 96, 257529, 365 63, 365103

Abstract:

A programmable device includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

US Patent:

8184465, May 22, 2012

Filed:

Oct 25, 2010

Appl. No.:

12/911379

Inventors:

William R. Tonti - Essex Junction VT, US
Wayne S. Berry - Essex Junction VT, US
John A. Fifield - Underhill VT, US
William H. Guthrie - Essex Junction VT, US
Richard S. Kontra - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 17/00

US Classification:

365 96, 257529, 257E23149, 3652257

Abstract:

A programmable device includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

US Patent:

20070298526, Dec 27, 2007

Filed:

Jun 26, 2007

Appl. No.:

11/768208

Inventors:

Wayne Berry - Essex Junction VT, US
John Fifield - Underhill VT, US
William Guthrie - Essex Junction VT, US
Richard Kontra - Williston VT, US
William Tonti - Essex Junction VT, US

International Classification:

G01R 31/26

US Classification:

438014000, 257E21001

Abstract:

A design structure for designing and manufacturing a programmable device. The design structure includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

US Patent:

20120178239, Jul 12, 2012

Filed:

Mar 22, 2012

Appl. No.:

13/427162

Inventors:

William R. Tonti - Essex Junction VT, US
Wayne S. Berry - Essex Junction VT, US
John A. Fifield - Underhill VT, US
William H. Guthrie - Essex Junction VT, US
Richard S. Kontra - Williston VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768

US Classification:

438467, 257E21592

Abstract:

A programmable device includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

US Patent:

54204569, May 30, 1995

Filed:

Feb 9, 1994

Appl. No.:

8/193927

Inventors:

Duane E. Galbi - Jericho VT
William H. Guthrie - Essex Junction VT
Oliver Kiehl - Essex Junction VT
Jack A. Mandelman - Essex Junction VT
Josef S. Watts - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 720

US Classification:

257529

Abstract:

A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse.

US Patent:

51260069, Jun 30, 1992

Filed:

May 31, 1991

Appl. No.:

7/708608

Inventors:

John E. Cronin - Milton VT
Paul A. Farrar - Burlington VT
Robert M. Geffken - Burlington VT
William H. Guthrie - Essex Junction VT
Carter W. Kaanta - Colchester VT
Rosemary A. Previti-Kelly - Richmond VT
James G. Ryan - Essex Junction VT
Ronald R. Uttecht - Essex Junction VT
Andrew J. Watts - Milton VT

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

B44C 122
C03C 1500
B29C 3700
C23F 100

US Classification:

156643

Abstract:

A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities.

US Patent:

49125478, Mar 27, 1990

Filed:

Jan 30, 1989

Appl. No.:

7/303207

Inventors:

James A. Bilowith - Colchester VT
Edward J. Dombroski - Jericho VT
William H. Guthrie - Essex Junction VT
Richard W. Noth - Fairfax VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2312
H01L 2348
H01L 2302

US Classification:

357 80

Abstract:

Multiple, single conductor, tape automated bonding (TAB) tapes are sequentially applied to a semiconductor device by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads on a semiconductor chip and to selected contacts on a lead frame followed by the laying down of at least one additional etched, single layer TAB tape which is then bonded to an inner row of bonding pads on the semiconductor chip and to different selected lead frame contacts. If desired the subsequent TAB tape may be adhered to the preceding TAB tape to increase the mechanical strength of all the tapes and improve the electrical characteristics of the tapes. The application of one or more ground planes to the assembly is also shown.