William D Guthrie

US Patent:

47027924, Oct 27, 1987

Filed:

Oct 28, 1985

Appl. No.:

6/791862

Inventors:

William L. Guthrie - Hopewell Junction NY
Frank B. Kaufman - Amawalk NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C23F 100
H05K 326
H01L 7184

US Classification:

156628

Abstract:

The present invention discloses a method of forming fine conductive lines, patterns, and connectors, and is particularly useful in the formation of electronic devices. The method comprises a series of steps in which: a polymeric material is applied to a substrate; the polymeric material is patterned to form openings through, spaces within, or combinations thereof in the polymeric material; subsequently, conductive material is applied to the patterned polymeric material, so that it at least fills the openings and spaces existing in the polymeric material; and excess conductive material is removed from the exterior major surface of the polymeric material using chemical-mechanical polishing, to expose at least the exterior major surface of the polymeric material. The structure remaining has a planar exterior surface, wherein the conductive material filling the openings and spaces in the patterned polymeric material becomes features such as fine lines, patterns, and connectors which are surrounded by the polymeric material. The polymeric material may be left in place as an insulator or removed, leaving the conductive features on the substrate.

US Patent:

47896485, Dec 6, 1988

Filed:

Oct 28, 1985

Appl. No.:

6/791887

Inventors:

Melanie M. Chow - Poughquag NY
John E. Cronin - Milton VT
William L. Guthrie - Hopewell Junction NY
Carter W. Kaanta - Essex Junction VT
Barbara Luther - Devon PA
William J. Patrick - Newburgh NY
Kathleen A. Perry - Lagrangeville NY
Charles L. Standley - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21304
H01L 21306

US Classification:

437225

Abstract:

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization.

US Patent:

56331959, May 27, 1997

Filed:

Sep 22, 1995

Appl. No.:

8/532376

Inventors:

William L. Guthrie - Hopewell Junction NY
Naftali E. Lustig - Croton on Hudson NY

Assignee:

International Business Machines, Corp. - Hopewell Junction NY

International Classification:

H01L 2126

US Classification:

438662

Abstract:

A method of laser planarizing metallic thin films minimizes the laser fluences required to melt or nearly melt the metalization. This is accomplished by reducing the optical reflectivity of the metallic lines and vias by using textured thin films. This reduction of optical reflectivity, in turn, reduces the minimum fluence needed to melt or nearly melt the metal using a laser, thus improving the process window and minimizing the damage to the surrounding media.