William G Keyes

US Patent:

8230278, Jul 24, 2012

Filed:

Nov 26, 2007

Appl. No.:

11/944855

Inventors:

Charles Lutz - Flowery Branch GA, US
Jason Spielvogel - Wheeling WV, US
Nicole Nall - Lithonia GA, US
Barron Cain - Roswell GA, US
William Keyes - Dacula GA, US
Gregory Irwin - Duluth GA, US

Assignee:

AT&T Intellectual Property, I, LP - Atlanta GA

International Classification:

G01R 31/28

US Classification:

714724, 370242

Abstract:

A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals.

US Patent:

8443245, May 14, 2013

Filed:

Jun 26, 2012

Appl. No.:

13/533308

Inventors:

Charles Lutz - Flowery Branch GA, US
Jason Spielvogel - Wheeling WV, US
Nicole Nall - Lithonia GA, US
Barron Cain - Roswell GA, US
William Keyes - Dacula GA, US
Gregory Irwin - Duluth GA, US

Assignee:

AT&T Intellectual Property I, L.P. - Atlanta GA

International Classification:

G01R 31/28

US Classification:

714724, 370242

Abstract:

A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals.