William T Larson

US Patent:

55808140, Dec 3, 1996

Filed:

Sep 11, 1995

Appl. No.:

8/527175

Inventors:

William L. Larson - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

H01L 2170
H01L 2700

US Classification:

437 52

Abstract:

A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

US Patent:

53716990, Dec 6, 1994

Filed:

Nov 17, 1992

Appl. No.:

7/977825

Inventors:

William L. Larson - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 1122

US Classification:

365145

Abstract:

A non-volatile ferroelectric memory having folded bit lines both reduces the size of the memory while also eliminating noise interference commonly associated with non-volatile ferroelectric memories having an open bit line architecture. The memory provides two pairs of coincident word and plate lines associated with each row, viz. , plate line A paired with word line B, and plate line B paired with word line A. The plate line of a pair may overlie or underlie the word line of the pair, and one may have the same width or a different width as the other of the pair, but preferably the elements of the pair are generally aligned, and the elements of the other pair are aligned with themselves, the two pairs being distally spaced apart. Each cell in the row is connected at the appropriate location to a word line of one of the pairs and a plate line of the other pair. Therefore, the word line and plate line of any single cell are not coincident.

US Patent:

54951178, Feb 27, 1996

Filed:

Jun 10, 1994

Appl. No.:

8/257954

Inventors:

William L. Larson - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

H01L 2978
H01L 2992
H01L 5100
H01G 706

US Classification:

257295

Abstract:

A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

US Patent:

52067882, Apr 27, 1993

Filed:

Dec 12, 1991

Appl. No.:

7/806726

Inventors:

William Larson - Colorado Springs CO
Thomas Davenport - Colorado Springs CO
Constance DeSmith - Colorado Springs CO

Assignee:

Ramtron Corporation - Colorado Springs CO

International Classification:

H01G 101
H01L 300
H01L 2702

US Classification:

361313

Abstract:

A ferroelectric capacitor for a memory device including a substrate, a bottom electrode and a top electrode. Between the bottom and top electrodes is either an alternating plurality of layers of ferroelectric material and intermediate electrodes or a plurality of layers of ferroelectric material. A method for forming the same through establishing one layer over the other is also disclosed.

US Patent:

50051024, Apr 2, 1991

Filed:

Jun 20, 1989

Appl. No.:

7/368668

Inventors:

William L. Larson - Colorado Springs CO

Assignee:

Ramtron Corporation - Colorado Springs CO

International Classification:

H01G 101
H01L 300
H01L 2702

US Classification:

361313

Abstract:

Disclosed is a multilayer capacitor structure in an integrated circuit, including a first electrode constructed by forming at least one layer over a substrate and forming a plate layer over the previous layer(s). A dielectric layer is formed over this first electrode, and a second electrode is established over the dielectric layer by forming a plate layer over the dielectric layer, and forming at least one additional layer over the plate layer. Each layer may serve one or more functions. Also disclosed is a further embodiment including constructing a first electrode by forming at least one layer on a substrate, forming a plate layer over the previous layer(s), and forming a dielectric layer over the first electrode. The resulting structure is then heated, preferably in an oxygen ambient, to oxidize the lower layer. A second electrode can then be formed over the dielectric layer.

US Patent:

52165728, Jun 1, 1993

Filed:

Mar 19, 1992

Appl. No.:

7/853901

Inventors:

William Larson - Colorado Springs CO
Paul J. Schuele - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

H01G 406
H01G 900
H01G 700
G11C 1122

US Classification:

361313

Abstract:

A ferroelectric capacitor for use in integrated circuits and having an asymmetric operation. The capacitor has a bottom electrode, a layer of ferroelectric material over the bottom electrode, a dielectric spacer on the sides of the bottom electrode and ferroelectric material, and a top electrode over the layer of ferroelectric material. The bottom and top electrode are comprised of different materials. Alternatively, an ion implantation region is formed in the top surface of the layer of ferroeletric material. A method of forming the asymmetric ferroelectric capacitor is also disclosed.