William C Lo

US Patent:

6385738, May 7, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/280648

Inventors:

William Lo - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 11277

US Classification:

714 25, 714715

Abstract:

A physical layer device (PHY) device in an Ethernet LAN is configured to permit ease of testing of its transmitter logic. The PHY device comprises a reset extension circuit for latching on the clock signals from a phase-locked loop (PLL) after the PLL has stabilized upon power-up or reset. The PHY device transmits a known valid bit pattern for testing purposes. A signal analyzer receives the transmitted bit pattern from the PHY device and compares the received bit pattern with a known valid bit pattern. A match indicates the proper operation of the PHY device transmitter logic.

US Patent:

6462814, Oct 8, 2002

Filed:

Mar 15, 2000

Appl. No.:

09/526979

Inventors:

William K. Lo - San Jose CA

Assignee:

Schlumberger Technologies, Inc. - San Jose CA

International Classification:

G01N 2100

US Classification:

3562372, 3562375

Abstract:

Methods and apparatus for optically probing an electrical device while the device is operating under control of a tester of the kind that applies test vectors and that has a test head in which the device can be mounted. An optical probe system has a light delivery and imaging module that is configured to be docked to a test head and that has imaging optics and a fine scanner. An optical processing subsystem can generate an incoming beam of light to illuminate the device through an optical fiber to a fiber end in the module. The fiber end is mounted in a fixed position on the optical axis of the imaging optics, and the fiber end and imaging optics are mounted in a fixed position to the platform of the fine scanner. Operating the fine scanner moves the fiber end, the imaging optics, the optical axis, and the focal point as a rigid unit.

US Patent:

6496261, Dec 17, 2002

Filed:

Feb 8, 2000

Appl. No.:

09/500757

Inventors:

Kenneth R. Wilsher - Palo Alto CA
William K. Lo - San Jose CA

Assignee:

Schlumberger Technologies, Inc. - San Jose CA

International Classification:

G01B 902

US Classification:

356450, 356491

Abstract:

Optical interferometery is used to probe an integrated circuit device under test (DUT). During each cycle of a repetitive electrical test pattern applied to the DUT a reference pulse is provided at a fixed time relative to the test pattern, and a probe pulse is provided at a time scanned through the test pattern in the manner of equivalent time sampling. The probe and reference light pulses are each split to provide at least a second probe pulse and a second reference pulse. One probe pulse and one reference pulse interact with the DUT at the same physical location, but at displaced times with respect to each other. The second probe pulse and the second reference pulse travel an optical delay path with length controlled to compensate for motions of the DUT. The probe pulses are recombined and detected to provide a probe interference signal. The reference pulses are recombined and detected to provide a reference interference signal.

US Patent:

6515506, Feb 4, 2003

Filed:

May 3, 2000

Appl. No.:

09/564711

Inventors:

William Lo - Cupertino CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

H03K 19173

US Classification:

326 38, 326101, 370258

Abstract:

A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

US Patent:

6741097, May 25, 2004

Filed:

Nov 5, 2002

Appl. No.:

10/287528

Inventors:

William Lo - Cupertino CA

Assignee:

Iarvell International, Ltd. - Hamilton

International Classification:

H03K 19173

US Classification:

326 38, 326 40, 716 16

Abstract:

A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

US Patent:

6816505, Nov 9, 2004

Filed:

Feb 9, 2000

Appl. No.:

09/501556

Inventors:

Sehat Sutardja - Cupertino CA
William Lo - Cupertino CA

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04L 1266

US Classification:

370463, 370465

Abstract:

A network device comprises a first integrated circuit having fabricated thereon a media access controller and a first serializer interface in communication with the media access controller. A second integrated circuit is provided comprising a physical layer interface in communication with an external device and a second serializer interface in communication with physical layer interface and the first serializer interface. The first and second serializer interfaces each comprise a fiber channel physical layer device implemented in accordance with 1000 BASE-X.

US Patent:

6825672, Nov 30, 2004

Filed:

Jun 7, 2002

Appl. No.:

10/165467

Inventors:

William Lo - Cupertino CA
Yiqing Guo - Cupertino CA

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G01R 3111

US Classification:

324533, 324534

Abstract:

A cable testing system and method tests cable and determines status, cable length and reflection amplitude. The test module includes a pretest state machine that senses activity on the cable and enables testing if activity is not detected for a first period. A test state machine is enabled by the pretest state machine, transmits a test pulse on the cable, measures a reflection amplitude and calculates a cable length. The test module determines the status based on the measured amplitude and the calculated cable length. A lookup table includes a plurality of sets of reflection amplitudes as a function of cable length. The test module determines the status using the lookup table, the reflection amplitude and the cable length.

US Patent:

6831479, Dec 14, 2004

Filed:

Nov 5, 2002

Appl. No.:

10/287527

Inventors:

William Lo - Cupertino CA

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03K 19173

US Classification:

326 38, 326101, 370258

Abstract:

A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.