William C Loo

US Patent:

20020032796, Mar 14, 2002

Filed:

Jun 5, 2001

Appl. No.:

09/875234

Inventors:

William Van Loo - Palo Alto CA, US

International Classification:

G06F003/00

US Classification:

709/235000, 710/057000

Abstract:

A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller a piori know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

US Patent:

20020059442, May 16, 2002

Filed:

May 10, 2001

Appl. No.:

09/854294

Inventors:

William Van Loo - Palo Alto CA, US

International Classification:

G06F015/16

US Classification:

709/232000

Abstract:

A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgement for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

US Patent:

20020194418, Dec 19, 2002

Filed:

Apr 30, 2002

Appl. No.:

10/135555

Inventors:

Satyanarayana Nishtala - Cupertino CA, US
William Van Loo - Palo Alto CA, US
Zahir Ebrahim - Mountain View CA, US

Assignee:

Sun Microsystems, Inc.

International Classification:

G06F013/40

US Classification:

710/307000

Abstract:

A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

US Patent:

57377553, Apr 7, 1998

Filed:

Feb 12, 1997

Appl. No.:

8/797995

Inventors:

Zahir Ebrahim - Mountain View CA
Satyanarayana Nishtala - Cupertino CA
William Van Loo - Palo Alto CA
Kevin Normoyle - Mountain View CA
Leslie Kohn - Mountain View CA
Louis F. Coffin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

711141

Abstract:

A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

US Patent:

58453253, Dec 1, 1998

Filed:

Apr 13, 1993

Appl. No.:

8/046476

Inventors:

William Van Loo - Palo Alto CA
John Watkins - Sunnyvale CA
Robert Garner - San Jose CA
William Joy - Palo Alto CA
Joseph Moran - Santa Clara CA
William Shannon - Los Altos CA
Ray Cheng - Cupertino CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1516
G06F 1208

US Classification:

711135

Abstract:

Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache "Flush" logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.

US Patent:

57064636, Jan 6, 1998

Filed:

May 12, 1997

Appl. No.:

8/854418

Inventors:

Zahir Ebrahim - Mountain View CA
Satyanarayana Nishtala - Cupertino CA
William Van Loo - Palo Alto CA
Kevin Normoyle - Mountain View CA
Leslie Kohn - Mountain View CA
Louis F. Coffin - San Jose CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

395447

Abstract:

A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.

US Patent:

51192900, Jun 2, 1992

Filed:

Jul 16, 1990

Appl. No.:

7/554186

Inventors:

William V. Loo - Palo Alto CA
John Watkins - Sunnyvale CA
Joseph Moran - Santa Clara CA
William Shannon - Los Altos CA
Ray Cheng - Cupertino CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

395400

Abstract:

Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i. e. , two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

US Patent:

59192658, Jul 6, 1999

Filed:

May 28, 1996

Appl. No.:

8/653900

Inventors:

Satyanarayana Nishtala - Cupertino CA
William Van Loo - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 104

US Classification:

713400

Abstract:

A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC. sub. -- CLK) signal and a source-synchronous clock (SRC. sub. -- SYN. sub. -- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC. sub. -- SYN. sub. -- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC. sub. -- SYN. sub. -- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC. sub. -- SYN. sub. -- CLK signal.