William E Mcneil

US Patent:

6668332, Dec 23, 2003

Filed:

Feb 15, 2000

Appl. No.:

09/504367

Inventors:

William Lloyd McNeil - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 100

US Classification:

713500

Abstract:

Internal clock signals generated on a chip can be viewed externally by multiplexing the clock signals and functional output signals to pin that are used to view or access the functional output signals. JTAG facilities already provided on the chip are used to generate control signals that drive the multiplexers. By so doing no new input or output facilities are required to view the clock signals.

US Patent:

6834356, Dec 21, 2004

Filed:

Feb 15, 2000

Appl. No.:

09/504973

Inventors:

William Lloyd McNeil - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 104

US Classification:

713501, 713600, 716 4

Abstract:

An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock generation circuit whose clock outputs are varied in accordance with changes to the bit patterns. By using the same facility to provide JTAG and clock functions the output clocks provided by clock generation circuit on the chip can be varied without using additional pins or the output clocks themselves.

US Patent:

8166246, Apr 24, 2012

Filed:

Jan 31, 2008

Appl. No.:

12/023600

Inventors:

Guy Lynn Guthrie - Austin TX, US
Thomas Leo Jeremiah - Hillsborough NC, US
William Lloyd McNeil - Raleigh NC, US
Hugh Shen - Round Rock TX, US
William John Starke - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711118, 711E12017, 711E1202, 711E12041, 711E12049, 711E12052

Abstract:

A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.

US Patent:

55353339, Jul 9, 1996

Filed:

Mar 30, 1993

Appl. No.:

8/040317

Inventors:

James J. Allen - Raleigh NC
Ronald J. Cooper - Raleigh NC
Douglas H. Cox - Raleigh NC
William L. McNeil - Cary NC
Herbert Rivera-Sanchez - Durham NC
Terri L. Tomlinson - Louisburg NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520003

Abstract:

A system and method for controlling a communications adapter interface such that supplemental data can be interleaved with data being transferred. The interleaving is performed in a manner such that the supplemental data is transparent to the data mover portion of the communications adapter. The supplemental data can be transferred in either read or write cycles that are interleaved at the beginning, in the middle, or at the end of data bursts or block data transfers. As a result of the interleaving, the slave interface bus is more fully utilized because arbitration and bus ownership changes do not create unused cycles. The interleaving is accomplished by temporarily halting an existing transfer of data and transferring the requested supplemental data while the data transfer is halted. After the supplemental data is transferred, the transfer of the balance of the data block is then allowed to continue. In other words, the present invention "steals" a cycle from the data transferror and uses this cycle to transfer supplemental data.

US Patent:

57907145, Aug 4, 1998

Filed:

Nov 1, 1994

Appl. No.:

8/332961

Inventors:

William Lloyd McNeil - Apex NC
David Carl Frank - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K 932

US Classification:

382300

Abstract:

Scaling of video is performed using area weighted averaging of input pixels to calculate coefficients to multiply with luminescence and crominence of input pixels. Such coefficients are produced for both the vertical and horizontal scaling directions of the input video stream. When scaling down or scaling up, scaling is first performed in the vertical direction to produce partially scaled pixels, which are then utilized for scaling in the horizontal direction. When scaling up, a pre-interpolation or pre-replication process is utilized to double the inputted pixel grid which doubled pixel grid is then utilized to scale down to the desired pixel grid size, which is greater than the originally inputted pixel grid size.