William M Panos

US Patent:

20040176938, Sep 9, 2004

Filed:

Mar 6, 2003

Appl. No.:

10/383139

Inventors:

Franz Gisin - San Jose CA, US
William Panos - San Jose CA, US
Mahamud Khandokar - Pleasanton CA, US

Assignee:

Sanmina-SCI Corporation - Huntsville AL

International Classification:

G06F017/50

US Classification:

703/014000

Abstract:

A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the subcircuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.